Abstract: A method for managing bind-render-target commands in a tile-based architecture. The method includes receiving a requested set of bound render targets and a draw command. The method also includes, upon receiving the draw command, determining whether a current set of bound render targets includes each of the render targets identified in the requested set. The method further includes, if the current set does not include each render target identified in the requested set, then issuing a flush-tiling-unit-command to a parallel processing subsystem, modifying the current set to include each render target identified in the requested set, and issuing bind-render-target commands identifying the requested set to the tile-based architecture for processing. The method further includes, if the current set of render targets includes each render target identified in the requested set, then not issuing the flush-tiling-unit-command.

Abstract: A memory cell reconfiguration process is performed in accordance with the operational characteristic settings determined based upon the results of analysis and/or testing of memory cell operations. The memory circuit can include a plurality of memory cells and memory cell configuration controller. The memory cells store information associated with a variety of operations. The memory cell configuration controller coordinates selective enablement and disablement of each of the plurality of memory cells, which can be done on a subset or group basis (e.g., enables and/or disables memory cells on a word length or row by row basis). The address mapping can be adjusted so that the memory space appears continuous to external components. The memory cell configuration controller can also forward configuration information to upstream and/or downstream components that can adjust operations to compensate for the memory cell configuration (e.g., to prevent overflow).

Abstract: A pixel processing system and method which permits rendering of complicated three dimensional images using a shallow graphics pipeline including reduced gate counts and low power operation. Pixel packet information includes pixel surface attribute values retrieved in a single unified data fetch stage. A determination is made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values may be performed). The pixel packet information processing is handled in accordance with results of the determining. The pixel surface attribute values and pixel packet information are removed from further processing if the pixel surface attribute values are occluded. In one exemplary implementation, the pixel packet includes a plurality of rows and the handling is coordinated for the plurality of rows.

Abstract: A system and method for correcting image data. Embodiments of the present invention provide image correction to overcome various lens effects, optical crosstalk, and electrical crosstalk. In one embodiment, the method includes accessing, within an electronic system, a plurality of control points for a patch of a spline surface and calculating a plurality of intermediate control points corresponding to a row of pixels of the patch. The method further includes receiving a pixel of an image and correcting the pixel based on the plurality of intermediate control points in streaming scanline column-wise or row-wise order.

Abstract: One embodiment of the present invention sets forth a technique for generating and transmitting video frame data from a graphics processing unit (GPU) to a color field sequential display device. A frame buffer image comprising per-pixel packed color channels is transformed to a frame buffer image comprising regions corresponding to the color channels with vertical blanking regions inserted between color sub-field regions. Each region of the transformed frame buffer image is sequentially transmitted to the color field sequential display device for display of the corresponding color channel. Backlight illumination for each color channel is controlled by the GPU for temporal alignment with display of each color channel during a vertical blanking interval. The GPU may compensate an individual pixel's color channel value based on a corresponding previous color channel value in order to minimize crosstalk between neighboring color fields.

Abstract: One embodiment of the present invention sets forth a technique for synchronization between two or more processors. The technique implements a spinlock acquire function and a spinlock release function. A processor executing the spinlock acquire function advantageously operates in a low power state while waiting for an opportunity to acquire spinlock. The spinlock acquire function configures a memory monitor to wake up the processor when spinlock is released by a different processor. The spinlock release function releases spinlock by clearing a lock variable and may clear a wait variable.

Abstract: A method and system for remapping units that are disabled to active units in a 3-D graphics pipeline. Specifically, in one embodiment, a method remaps processing elements in a pipeline of a graphics pipeline unit. Graphical input data are received. Then the number of enabled processing elements are determined from a plurality of processing elements. Each of the enabled processing elements are virtually addressed above a translator to virtually process the graphical input data. Then, the virtual addresses of each of the enabled processing elements are mapped to physical addresses of the enabled processing elements at the translator. The graphical input data are physically processed at the physical addresses of the enabled processing elements. In addition, each of the enabled processing elements are physically addressed below the translator to further process the graphical input data.

Abstract: Embodiments of the invention provide methods and configuration for packaging multiple semiconductor ships in a semiconductor package. In one embodiment, an integrated circuit system includes a printed circuit board, a first MOSFET device disposed on a first surface of the printed circuit board, and a second MOSFET device disposed on a second surface of the printed circuit board, wherein the first MOSFET device overlaps an edge of the second MOSFET device in a direction extending through the printed circuit board.

Abstract: An apparatus for determining an electrical reliability of a ball grid array (BGA) assembly of an integrated circuit is presented. The assembly comprises a testing printed circuit board (PCB) having an integrated circuit (IC) test region located thereon. Vias extend through the testing PCB from a surface to an underside thereof within the IC test region. Each via has an IO pad or ground pad electrically connectable thereto. An IC package having an IC die connected thereto by solder bumps is connected to the IC test region by solder balls, such that each of the IO pads is electrically connectable to a respective pair of the solder balls and solder bumps by the vias. A method of testing interconnection reliability of the BGA using the apparatus is also presented.

Abstract: A system and method for image capture. The method includes configuring an image sensor to capture at a full resolution of the image sensor and automatically capturing a first image with the image sensor irrespective of a shutter button of a camera. The method further includes receiving an image capture request and accessing a second image after the receiving of the image capture request. The first image is captured prior to the receiving of the image capture request. The first image and the second image may then be stored.

Abstract: A quick-resume gaming system includes a game device configured to support playing a video game by a user. The quick-resume gaming system also includes a gaming control module coupled to the game device and configured to suspend and resume playing of the video game at a current display frame based on user initiated suspend and resume control commands, respectively. In another aspect, a method of quick-resume gaming includes playing a video game on a game device by a user. The method of quick-resume gaming also includes suspending the playing of the video game on the game device at a current display frame based on the user initiating a suspend control command and resuming the playing of the video game on the game device at the current display frame based on the user initiating a resume control command.

Abstract: A method includes registering one or more target computing device(s) with a request processing module of a server computing device and an application executing on a client computing device communicatively coupled to the server computing device, and initiating, through the application, a request to configure a hardware setting on the one or more target computing device(s) based on a communication mechanism. The method also includes processing, through the request processing module, the request to generate a validated message related to the hardware setting configuration and to extract information related to identifiers of the one or more target computing device(s), a hardware thereof and the hardware setting. Further, the method includes redirecting the validated message to the one or more target computing device(s) along with the extracted information, and interpreting the received validated message and the extracted information at the one or more target computing device(s).

Abstract: A parallel processing subsystem includes a plurality of general processing clusters (GPCs). Each GPC includes one or more clipping, culling, viewport transformation, and perspective correction engines (VPC). Since VPCs are distributed per GPC, each VPC can process graphics primitives in parallel with the other VPCs processing graphics primitives.

Abstract: A method for synchronizing an input data stream with an output data stream in a video processor. The method includes receiving an input data stream and receiving an output data stream, wherein the input data stream and the output data stream each comprise a plurality of pixels. The method further includes sequentially storing pixels of the input data stream using an input buffer and sequentially storing pixels of the output data stream using an output buffer. Timing information is determined by examining the input data stream and the output data stream. A synchronization adjustment is applied to the input buffer and the output buffer in accordance with the timing information. Pixels are output from the input buffer and the output buffer to produce a synchronized mixed video output stream.

Abstract: Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.

Abstract: One embodiment of the present invention includes approaches for processing graphics primitives associated with cache tiles when rendering an image. A set of graphics primitives associated with a first render target configuration is received from a first portion of a graphics processing pipeline, and the set of graphics primitives is stored in a memory. A condition is detected indicating that the set of graphics primitives is ready for processing, and a cache tile is selected that intersects at least one graphics primitive in the set of graphics primitives. At least one graphics primitive in the set of graphics primitives that intersects the cache tile is transmitted to a second portion of the graphics processing pipeline for processing. One advantage of the disclosed embodiments is that graphics primitives and associated data are more likely to remain stored on-chip during cache tile rendering, thereby reducing power consumption and improving rendering performance.

Abstract: One embodiment of the present invention sets forth a technique for parallel distribution of primitives to multiple rasterizers. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives from the multiple geometry units concurrently to multiple rasterizers at rates of multiple primitives per clock. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.

Abstract: Described are methods and systems for processing data. A motion estimator uses a block of an input frame of video data and a block of a reference frame of video data to generate motion vectors according to a first encoding scheme. A motion compensator produces half pel motion vectors from the motion vectors according to a second encoding scheme that is different from the first encoding scheme.

Abstract: A memory access technique, in accordance with one embodiment of the present invention, includes caching page size data for use in accessing a set-associative translation lookaside buffer (TLB). The technique utilizes a translation lookaside buffer data structure that includes a page size table and a translation lookaside buffer. Upon receipt of a memory access request a page size is looked-up in the page size table utilizing the page directory index in the virtual address. A set index is calculated utilizing the page size. A given set of entries is then looked-up in the translation lookaside buffer utilizing the set index. The virtual address is compared to each TLB entry in the given set. If the comparison results in a TLB hit, the physical address is received from the matching TLB entry.

Abstract: The present invention permits an I/O port to be used with a variety of different I/O devices, regardless of their device type implementation. Thus, one set of pins may be used for various different I/O devices.