Patents Assigned to NVidia
  • Patent number: 8704830
    Abstract: One embodiment of the present invention sets forth a technique for improving path rendering on computer systems by efficiently representing and computing sub-pixel coverage for path objects. A stencil buffer is configured to store multiple stencil samples per pixel stored in an image buffer. The stencil samples undergo stencil testing to produce a set of Boolean values per pixel, which collectively define a geometric coverage percentage for the pixel. The coverage percentage is used to modulate a color value for the pixel. The modulated color value is then blended into the image buffer as an anti-aliased pixel. This technique advantageously enables efficient anti-aliasing for path rendering.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: April 22, 2014
    Assignee: Nvidia Corporation
    Inventors: Mark J. Kilgard, Patrick R. Brown
  • Publication number: 20140105260
    Abstract: One aspect provides a method of handling a proactive indication received from a subscriber identity module at a modem, the modem being connected to a terminal equipment via a command interface. The method comprises receiving, at a modem processor, the proactive indication from the subscriber identity module. The method further comprises determining that the indication is to be handled by the modem processor. The method further comprises a modem processor transmitting a display command via the command interface to the terminal equipment and the modem processor awaiting a user response command, and continuing or aborting an action indicated in the proactive indication depending on the user response in the user response command received from the terminal equipment.
    Type: Application
    Filed: April 8, 2013
    Publication date: April 17, 2014
    Applicant: NVIDIA Corporation
    Inventor: Alexander May-Weymann
  • Publication number: 20140104267
    Abstract: Techniques are disclosed for suppressing access to a depth processing unit associated with a graphics processing pipeline. The method includes receiving a graphics primitive from a first pipeline stage associated with the graphics processing pipeline. The method further includes determining that the graphics primitive is visible over one or more graphics primitives previously rendered to a frame buffer, and determining that the depth buffer is in a read-only mode. The method further includes suppressing an operation to transmit the graphics primitive to the depth processing unit. One advantage of the disclosed technique is that power consumption is reduced within the GPU by avoiding unnecessary accesses to the depth processing unit.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Christian AMSINCK, Christian ROUET, Tony LOUCA
  • Publication number: 20140109102
    Abstract: A multi-threaded processing unit includes a hardware pre-processor coupled to one or more processing engines (e.g., copy engines, GPCs, etc.) that implement pre-emption techniques by dividing tasks into smaller subtasks and scheduling subtasks on the processing engines based on the priority of the tasks. By limiting the size of the subtasks, higher priority tasks may be executed quickly without switching the context state of the processing engine. Tasks may be subdivided based on a threshold size or by taking into account other consideration such as physical boundaries of the memory system.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Samuel H. Duncan, Gary WARD, M. Wasiur RASHID, Lincoln G. GARLICK, Wojciech Jan Truty
  • Publication number: 20140105513
    Abstract: A method for compressing graphics data comprises selecting z-planes from a plurality of z-planes. The selected z-planes are predictor z-planes. A residual is determined for each sample not covered by one of the predictor z-planes. A sample is covered by one of the predictor z-planes when the predictor z-plane correctly defines a z-value of the sample. A residual comprises a value that is a difference between a predicted z-value provided by one of the predictor z-planes and an actual z-value for the sample. The predictor z-planes and the residuals are stored in a z-buffer.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Bengt-Olaf Schneider, Christian Amsinck
  • Publication number: 20140104450
    Abstract: A digital camera includes an image optimization engine configured to generate an optimized image based on a raw image captured by the digital camera. The image optimization engine implements one or more machine learning engines in order to select rendering algorithms and rendering algorithm arguments that may then be used to render the raw image.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: Michael Brian COX
  • Publication number: 20140108940
    Abstract: A system and method for communicating over a network are presented. Embodiments of the present invention are operable to capture a touch input directly from an electronic visual display coupled to a client device. The touch inputs are then transmitted from the client device to a host device over a network. The host device proceeds to render data in response to the touch input provided by the client device, which is then transmitted back to the client device over the network for display on the client device.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Dwight Diercks, Franck Diard
  • Publication number: 20140105259
    Abstract: A modem and a method of handling a proactive software toolkit command. In one embodiment, the modem includes: (1) a digital interface configured to receive from a subscriber information module a proactive software toolkit command the modem is designated by standard to handle and (2) a command processor coupled to the digital interface and configured to prepare information regarding the command for transmission to terminal equipment coupled to the modem.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: Alexander May-Weymann
  • Publication number: 20140105272
    Abstract: A technique for decoding data within a context-based adaptive binary arithmetic coding (CABAC) stream processes one or more bins of compressed data based on video format parameters associated with the stream. A configurable CABAC decoder circuit cascades one or more instances of CABAC bin decoder logic to operate properly within a timing constrain established by a decoder clock frequency. The decoder may advantageously select among different combinations of decoder clock frequency and decoded bins per clock cycle to minimize power consumption associated with decompressing and playing the compressed data.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ravi BULUSU, HARIKRISHNA REDDY
  • Publication number: 20140104242
    Abstract: A system and method are provided for displaying a video signal concurrently on a plurality of display devices. The system includes an operating system (OS) and a device driver. The device driver identifies a subset of display devices connected to the system, where the subset includes two or more of the display devices. The device driver also connects to the OS a virtual display device that is representative of the subset of display devices. The device driver further configures the system to route a video signal to all of the subset of display devices.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Applicant: Nvidia Corporation
    Inventors: Adrian Muntianu, Rajat Agarwal
  • Patent number: 8698908
    Abstract: A rolling shutter digital camera. Each photographic image of a given exposure duration is captured as a multi-frame burst of frames each having a shorter exposure duration to minimize motion blur and to reduce sensor noise by averaging. Each frame is quantized into swaths, captured sequentially by the rolling shutter. Swaths of the first frames are analyzed to select a set of best motion detection reference regions. Swaths of subsequent frames are analyzed versus only those regions, to reduce required computation, and are re-registered accordingly. Corresponding swaths of each frame are accumulated. The accumulator is normalized to the desired bit depth and written as the final image. Averaging of the multiple frames is improved by re-registering swaths rather than entire frames, because of the time delta caused by the rolling shutter.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: April 15, 2014
    Assignee: Nvidia Corporation
    Inventor: Keith R. Slavin
  • Patent number: 8698802
    Abstract: One embodiment of the present invention sets forth technique for watertight tessellation in a displaced subdivision surface. A subdivision surface is represented as a novel parametric quad patch that is continuous with respect to position (C0) and partial derivatives (C1) along boundaries as well as interior regions. The novel parametric quad patch is referred to herein as a Hermite Gregory patch and comprises a Hermite patch augmented to include a pair of twist vector parameters per vertex. Each pair of twist vectors is combined into one twist vector during evaluation, according to weights based on proximity to parametric boundaries. Evaluation yields an approximation mesh comprising a position for each vertex and a corresponding normal vector for the vertex. Displacement is performed based on the approximation mesh and a displacement map to generate a displaced approximation mesh that is reflective of the displaced subdivision surface.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: April 15, 2014
    Assignee: Nvidia Corporation
    Inventors: Henry Packard Moreton, Ignacio Castaño Aguado, Kirill Dmitriev
  • Patent number: 8698305
    Abstract: A multi-configuration interface device for coupling different types of GPUs (graphics processor units) to a PCB (printed circuit board). The interface device comprises a GPU interface for a connection to the GPU and a PCB interface for a connection to the PCB. The GPU interface is implemented using a customizable attachment footprint for effectuating a connection to differing GPU types while maintaining the PCB interface for the connection to the PCB. The ball array for different GPUs can be configured to respectively support them. The interface device maintains a consistent PCB interface. Thus, as GPU characteristics change and evolve, or as different GPU versions are implemented, a consistent connection can be maintained for the PCB.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: April 15, 2014
    Assignee: Nvidia Corporation
    Inventors: Thomas E. Dewey, James K. Dobbins, Joseph S. Minacapelli, Simon A. Thomas
  • Patent number: 8701091
    Abstract: A method and system for application development. Specifically, a generic console interface is provided that is capable of interacting with graphics applications. The console interface is capable of accessing a graphics application by detouring at least one predefined system call made by the graphics application. User input is intercepted that is related to the predefined system call that is detoured. The user input is communicated through the console interface. An operation is performed as implemented by the user input through a dynamically loadable module.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: April 15, 2014
    Assignee: Nvidia Corporation
    Inventors: Matthias M. Wloka, Raul Aguaviva, Sebastien Julien Domine, Gregory E. James, William Orville Ramey, II
  • Patent number: 8698825
    Abstract: A system, method, and computer program product are provided for optimizing use of a vertex cache. In use, information is identified, where such information is associated with vertex data stored in a vertex cache. To this end, use of the vertex cache may be optimized utilizing the information. In one embodiment, the information may include new information derived from the vertex data, and optionally index data, prior to processing of the vertex data. Further, the vertex cache may optionally utilize the information to optimize performance of the vertex cache by minimizing a number of cache misses.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: April 15, 2014
    Assignee: NVIDIA Corporation
    Inventors: Tuomas J. Lukka, Tero T. Karras, Jan H. Achrenius
  • Patent number: 8698918
    Abstract: Embodiments of the claimed subject matter are directed to methods for automatic white balancing in an image-capture device. In one embodiment, given an estimated illuminant color (e.g., derived from the Gray World method), a more optimal illuminant color can be found by projecting this point to a plot of common illuminants to determine the closest point on the plot of common illuminants. Once the closest point of the plot of common illuminants is derived, the actual image (e.g., pixel) data of the scene is adjusted by the value of the closest point on the plot of common illuminants so that the light is normalized for the scene.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: April 15, 2014
    Assignee: Nvidia Corporation
    Inventors: Amnon Silverstein, Brian Cabral
  • Patent number: 8698808
    Abstract: One embodiment of the present invention sets forth a technique for converting dashed strokes into quadratic Bèzier segment sequences. Path rendering with stroking and dashing may be accelerated when a graphics processing unit or other processor is configured to subdivide quadratic Bèzier segments based on the remaining distance for a current dash pattern element and the arc length of the current quadratic Bèzier path segment to generate “on” dash pattern segments. Each “on” dash pattern segment is then bounded by a conservative geometric hull. A point containment technique is then used to identify pixels within each conservative geometric hull that are within half of the stroke width of any point along a path to be stroked.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: April 15, 2014
    Assignee: Nvidia Corporation
    Inventor: Mark J. Kilgard
  • Patent number: 8698817
    Abstract: A video processor for executing video processing operations. The video processor includes a host interface for implementing communication between the video processor and a host CPU. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A scalar execution unit is coupled to the host interface and the memory interface and is configured to execute scalar video processing operations. A vector execution unit is coupled to the host interface and the memory interface and is configured to execute vector video processing operations.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: April 15, 2014
    Assignee: Nvidia Corporation
    Inventors: Shirish Gadre, Ashish Karandikar, Stephen D. Lew, Christopher T. Cheng
  • Patent number: 8698917
    Abstract: In an embodiment, computational complexity of estimating the actual illuminant of a scene is reduced by examining only a subset of the pixel values generated for a received image frame. In another embodiment, number of rotations of color values is minimized by selecting an area which contains the color cue values of a color in an original/unrotated coordinate space and has boundaries which parallel the axis of the original coordinate space, and rotating a color value only if the color value is within the selected area. In another embodiment, such an area is used in conjunction with a histogram-based approach to determine the actual illuminant.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: April 15, 2014
    Assignee: Nvidia Corporation
    Inventor: Anurag Goel
  • Patent number: 8700925
    Abstract: Metrics representing a combined measure of power used by a central processing unit (CPU) and power used by a graphics processing unit (GPU) are compared to a shared supply power and thermal power budgets. Power used by the CPU and power used by the GPU are regulated in tandem using a fuzzy logic control system that can implement fuzzy rules that describe the management within thermal and supply power design constraints of the platform.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: April 15, 2014
    Assignee: Nvidia Corporation
    Inventor: David Wyatt