Patents Assigned to NVidia
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Patent number: 8706975Abstract: A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for coordinating context memory storage block binds and independently controlling access to the context memory without interference from other engine activities. In one exemplary implementation the context information is included in a block and the memory management unit binds the block to instance memory. The instance memory can be protected memory. The instance memory can also support multiple channels associated with the plurality of engines. In one exemplary implementation, the instance memory includes a pointer to a page table. The instance memory can also include context save and restore data and each one of the plurality of engines initiates a unique block bind by indicating an association between their engine ID and a given block of instance memory.Type: GrantFiled: November 1, 2006Date of Patent: April 22, 2014Assignee: Nvidia CorporationInventors: David B. Glasco, John S. Montrym, Lingfeng Yuan
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Patent number: 8704275Abstract: A die micro electro-mechanical switch management system and method facilitate power conservation by selectively preventing electrical current from flowing in designated components. A present invention semiconductor die comprises a block of transistors for performing switching operations, a bus (e.g., a power bus, a signal bus, etc.) for conveying electrical current and a micro electro-mechanical switch that couples and decouples the block of transistors to and from the bus. The micro electro-mechanical switch is opened and closed depending upon operations (e.g., switching operations) being performed by the block of transistors. Electrical current is prevented from flowing to the block of transistors when the micro electro-mechanical switch is open and the block of transistors is electrically isolated. The micro electro-mechanical switch can interrupt electrical current flow in a plurality of the bus lines and/or can be included in a relay array.Type: GrantFiled: December 28, 2007Date of Patent: April 22, 2014Assignee: Nvidia CorporationInventor: Michael B. Diamond
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Patent number: 8704830Abstract: One embodiment of the present invention sets forth a technique for improving path rendering on computer systems by efficiently representing and computing sub-pixel coverage for path objects. A stencil buffer is configured to store multiple stencil samples per pixel stored in an image buffer. The stencil samples undergo stencil testing to produce a set of Boolean values per pixel, which collectively define a geometric coverage percentage for the pixel. The coverage percentage is used to modulate a color value for the pixel. The modulated color value is then blended into the image buffer as an anti-aliased pixel. This technique advantageously enables efficient anti-aliasing for path rendering.Type: GrantFiled: May 19, 2011Date of Patent: April 22, 2014Assignee: Nvidia CorporationInventors: Mark J. Kilgard, Patrick R. Brown
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Publication number: 20140105513Abstract: A method for compressing graphics data comprises selecting z-planes from a plurality of z-planes. The selected z-planes are predictor z-planes. A residual is determined for each sample not covered by one of the predictor z-planes. A sample is covered by one of the predictor z-planes when the predictor z-plane correctly defines a z-value of the sample. A residual comprises a value that is a difference between a predicted z-value provided by one of the predictor z-planes and an actual z-value for the sample. The predictor z-planes and the residuals are stored in a z-buffer.Type: ApplicationFiled: October 15, 2012Publication date: April 17, 2014Applicant: NVIDIA CORPORATIONInventors: Bengt-Olaf Schneider, Christian Amsinck
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Publication number: 20140105260Abstract: One aspect provides a method of handling a proactive indication received from a subscriber identity module at a modem, the modem being connected to a terminal equipment via a command interface. The method comprises receiving, at a modem processor, the proactive indication from the subscriber identity module. The method further comprises determining that the indication is to be handled by the modem processor. The method further comprises a modem processor transmitting a display command via the command interface to the terminal equipment and the modem processor awaiting a user response command, and continuing or aborting an action indicated in the proactive indication depending on the user response in the user response command received from the terminal equipment.Type: ApplicationFiled: April 8, 2013Publication date: April 17, 2014Applicant: NVIDIA CorporationInventor: Alexander May-Weymann
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Publication number: 20140104450Abstract: A digital camera includes an image optimization engine configured to generate an optimized image based on a raw image captured by the digital camera. The image optimization engine implements one or more machine learning engines in order to select rendering algorithms and rendering algorithm arguments that may then be used to render the raw image.Type: ApplicationFiled: October 12, 2012Publication date: April 17, 2014Applicant: NVIDIA CORPORATIONInventor: Michael Brian COX
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Publication number: 20140104242Abstract: A system and method are provided for displaying a video signal concurrently on a plurality of display devices. The system includes an operating system (OS) and a device driver. The device driver identifies a subset of display devices connected to the system, where the subset includes two or more of the display devices. The device driver also connects to the OS a virtual display device that is representative of the subset of display devices. The device driver further configures the system to route a video signal to all of the subset of display devices.Type: ApplicationFiled: October 12, 2012Publication date: April 17, 2014Applicant: Nvidia CorporationInventors: Adrian Muntianu, Rajat Agarwal
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Publication number: 20140104267Abstract: Techniques are disclosed for suppressing access to a depth processing unit associated with a graphics processing pipeline. The method includes receiving a graphics primitive from a first pipeline stage associated with the graphics processing pipeline. The method further includes determining that the graphics primitive is visible over one or more graphics primitives previously rendered to a frame buffer, and determining that the depth buffer is in a read-only mode. The method further includes suppressing an operation to transmit the graphics primitive to the depth processing unit. One advantage of the disclosed technique is that power consumption is reduced within the GPU by avoiding unnecessary accesses to the depth processing unit.Type: ApplicationFiled: October 12, 2012Publication date: April 17, 2014Applicant: NVIDIA CORPORATIONInventors: Christian AMSINCK, Christian ROUET, Tony LOUCA
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Publication number: 20140109102Abstract: A multi-threaded processing unit includes a hardware pre-processor coupled to one or more processing engines (e.g., copy engines, GPCs, etc.) that implement pre-emption techniques by dividing tasks into smaller subtasks and scheduling subtasks on the processing engines based on the priority of the tasks. By limiting the size of the subtasks, higher priority tasks may be executed quickly without switching the context state of the processing engine. Tasks may be subdivided based on a threshold size or by taking into account other consideration such as physical boundaries of the memory system.Type: ApplicationFiled: October 12, 2012Publication date: April 17, 2014Applicant: NVIDIA CORPORATIONInventors: Samuel H. Duncan, Gary WARD, M. Wasiur RASHID, Lincoln G. GARLICK, Wojciech Jan Truty
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Publication number: 20140105272Abstract: A technique for decoding data within a context-based adaptive binary arithmetic coding (CABAC) stream processes one or more bins of compressed data based on video format parameters associated with the stream. A configurable CABAC decoder circuit cascades one or more instances of CABAC bin decoder logic to operate properly within a timing constrain established by a decoder clock frequency. The decoder may advantageously select among different combinations of decoder clock frequency and decoded bins per clock cycle to minimize power consumption associated with decompressing and playing the compressed data.Type: ApplicationFiled: October 11, 2012Publication date: April 17, 2014Applicant: NVIDIA CORPORATIONInventors: Ravi BULUSU, HARIKRISHNA REDDY
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Publication number: 20140108940Abstract: A system and method for communicating over a network are presented. Embodiments of the present invention are operable to capture a touch input directly from an electronic visual display coupled to a client device. The touch inputs are then transmitted from the client device to a host device over a network. The host device proceeds to render data in response to the touch input provided by the client device, which is then transmitted back to the client device over the network for display on the client device.Type: ApplicationFiled: October 15, 2012Publication date: April 17, 2014Applicant: NVIDIA CORPORATIONInventors: Dwight Diercks, Franck Diard
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Publication number: 20140105259Abstract: A modem and a method of handling a proactive software toolkit command. In one embodiment, the modem includes: (1) a digital interface configured to receive from a subscriber information module a proactive software toolkit command the modem is designated by standard to handle and (2) a command processor coupled to the digital interface and configured to prepare information regarding the command for transmission to terminal equipment coupled to the modem.Type: ApplicationFiled: October 17, 2012Publication date: April 17, 2014Applicant: NVIDIA CORPORATIONInventor: Alexander May-Weymann
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Patent number: 8698814Abstract: A mapping engine maps general processing clusters (GPCs) within a parallel processing subsystem to screen tiles on a display screen based on the number of enabled streaming multiprocessors (SMs) within each GPC. A given GPC then generates pixels for the screen tiles to which the GPC is mapped. One advantage of the disclosed technique is a given GPC performs a fraction of the processing tasks associated with the parallel processing subsystem that is roughly proportional to the fraction of SMs included within the GPC.Type: GrantFiled: October 13, 2009Date of Patent: April 15, 2014Assignee: Nvidia CorporationInventor: James M. Van Dyke
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Patent number: 8700925Abstract: Metrics representing a combined measure of power used by a central processing unit (CPU) and power used by a graphics processing unit (GPU) are compared to a shared supply power and thermal power budgets. Power used by the CPU and power used by the GPU are regulated in tandem using a fuzzy logic control system that can implement fuzzy rules that describe the management within thermal and supply power design constraints of the platform.Type: GrantFiled: September 1, 2009Date of Patent: April 15, 2014Assignee: Nvidia CorporationInventor: David Wyatt
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Patent number: 8698918Abstract: Embodiments of the claimed subject matter are directed to methods for automatic white balancing in an image-capture device. In one embodiment, given an estimated illuminant color (e.g., derived from the Gray World method), a more optimal illuminant color can be found by projecting this point to a plot of common illuminants to determine the closest point on the plot of common illuminants. Once the closest point of the plot of common illuminants is derived, the actual image (e.g., pixel) data of the scene is adjusted by the value of the closest point on the plot of common illuminants so that the light is normalized for the scene.Type: GrantFiled: December 30, 2009Date of Patent: April 15, 2014Assignee: Nvidia CorporationInventors: Amnon Silverstein, Brian Cabral
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Patent number: 8700387Abstract: Methods and systems for transcoding input audio data in a first encoding format to generate audio data in a second encoding format, and filterbanks for use in such systems. Some such systems include a combined synthesis and analysis filterbank (configured to generate transformed frequency-band coefficients indicative of at least one sample of the input audio data by transforming frequency-band coefficients in a manner equivalent to upsampling the frequency-band coefficients and filtering the resulting up-sampled values to generate the transformed frequency-band coefficients, where the frequency-band coefficients are partially decoded versions of input audio data that are indicative of the at least one sample) and a processing subsystem configured to generate transcoded audio data in the second encoding format in response to the transformed frequency-band coefficients.Type: GrantFiled: September 14, 2006Date of Patent: April 15, 2014Assignee: Nvidia CorporationInventors: Anil Ubale, Partha Sriram
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Patent number: 8700808Abstract: A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.Type: GrantFiled: December 28, 2007Date of Patent: April 15, 2014Assignee: NVIDIA CorporationInventors: Radoslav Danilak, Krishnaraj S. Rao
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Patent number: 8698802Abstract: One embodiment of the present invention sets forth technique for watertight tessellation in a displaced subdivision surface. A subdivision surface is represented as a novel parametric quad patch that is continuous with respect to position (C0) and partial derivatives (C1) along boundaries as well as interior regions. The novel parametric quad patch is referred to herein as a Hermite Gregory patch and comprises a Hermite patch augmented to include a pair of twist vector parameters per vertex. Each pair of twist vectors is combined into one twist vector during evaluation, according to weights based on proximity to parametric boundaries. Evaluation yields an approximation mesh comprising a position for each vertex and a corresponding normal vector for the vertex. Displacement is performed based on the approximation mesh and a displacement map to generate a displaced approximation mesh that is reflective of the displaced subdivision surface.Type: GrantFiled: October 5, 2010Date of Patent: April 15, 2014Assignee: Nvidia CorporationInventors: Henry Packard Moreton, Ignacio CastaƱo Aguado, Kirill Dmitriev
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Patent number: 8698908Abstract: A rolling shutter digital camera. Each photographic image of a given exposure duration is captured as a multi-frame burst of frames each having a shorter exposure duration to minimize motion blur and to reduce sensor noise by averaging. Each frame is quantized into swaths, captured sequentially by the rolling shutter. Swaths of the first frames are analyzed to select a set of best motion detection reference regions. Swaths of subsequent frames are analyzed versus only those regions, to reduce required computation, and are re-registered accordingly. Corresponding swaths of each frame are accumulated. The accumulator is normalized to the desired bit depth and written as the final image. Averaging of the multiple frames is improved by re-registering swaths rather than entire frames, because of the time delta caused by the rolling shutter.Type: GrantFiled: February 11, 2008Date of Patent: April 15, 2014Assignee: Nvidia CorporationInventor: Keith R. Slavin
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Patent number: 8698819Abstract: Embodiments for programming a graphics pipeline, and modules within the graphics pipeline, are detailed herein. One embodiment described a method of implementing software assisted shader merging for a graphics pipeline. The method involves accessing a first shader program in memory, and generating a first shader instruction from that program. This first instruction is loaded into an instruction table at a first location, indicated by an offset register. A second shader program in memory is then accessed, and used to generate a second shader instruction. The second shader instruction is loaded into the instruction table at a second location indicated by the offset register.Type: GrantFiled: August 15, 2007Date of Patent: April 15, 2014Assignee: NVIDIA CorporationInventors: Justin Michael Mahan, Edward A. Hutchins