Abstract: A system, method, and computer program product are provided for controlling warping of a substrate. In use, a first solder mask is attached to a top side of a substrate. Additionally, a second solder mask is attached to a bottom side of the substrate, wherein the first solder mask and the second solder mask control warping of the substrate.

Abstract: The invention discloses a method and a system for wireless transmission of content. The present invention relates generally to wireless network technology, Problems solved by the invention is that, the method for manually entering the shared key is neither convenient nor secure, while the method for transmitting the shared key over the wireless network also makes the shared key exposed to an unsafe environment. Embodiments of the invention provide the program as follows: a method and a system for wireless transmission of content, wherein, capturing shared key, using the shared key to encrypt the content, and then transmitting the encrypted content over the wireless network. Embodiments of the invention are suitable for terminals and devices wirelessly connected, and so on.

Abstract: A system and method for constructing a bounding volume hierarchical structure are disclosed. The method includes defining a parent node for the bounding volume hierarchical structure, the parent node including a parent node bounding volume enclosing a plurality of objects. A first cost is computed for performing an object partition of the parent node bounding volume to produce a first plurality of child node bounding volumes, and a second cost is also computed for performing a spatial partitioning of the parent node bounding volume to produce a second plurality of child node bounding volumes. The bounding volume hierarchical structure is constructed employing the second plurality of child node bounding volumes produced from the spatial partitioning of the parent node bounding volume if the second cost is lower than the first cost.

Abstract: A system, method, and computer program product are provided for affixing a post to a substrate pad. In use, a post is affixed to each of one or more pads of a substrate, where each post receives a ball of a package during an assembly process.

Abstract: A method for compressing framebuffer data is presented. The method includes determining a reduction ratio for framebuffer data in a tile including multiple samples. The reduction ratio determined is independent of the sampling mode, where the sampling mode is the number of samples within each pixel in the tile. The method further includes comparing a first portion of the framebuffer data for each of the multiple samples to determine an equality comparison result and also comparing a second portion of the framebuffer data for each one of the multiple samples to compute per-channel differences for each one of the multiple samples and testing the per-channel differences against a threshold value to determine a threshold comparison result. Finally, the method comprises compressing the framebuffer data for the tile based on the reduction ratio, the equality comparison result and the threshold comparison result to produce output framebuffer data for the tile.

Abstract: A memory access technique, in accordance with one embodiment of the present invention, includes coalescing mappings between virtual memory and physical memory when a contiguous plurality of virtual pages map to a contiguous plurality of physical pages. Any of the coalesced mappings are sufficient to map all pages within the coalesced region. Accordingly, a memory subsystem can cache a single coalesced mapping and not all of them. The single cached coalesced mapping may be used to translate all of the virtual addresses to physical addresses for the corresponding contiguous memory space.

Abstract: One embodiment of the present invention sets forth a technique for continuously adjusting a variable refresh rate to reduce the power consumption of a display device. The refresh rate of the display device tracks the effective frame rate of the content being displayed. As the effective frame rate of the content decreases, the refresh rate is lowered until a minimum value is reached. When the effective frame rate of the content equals the refresh rate, the refresh rate is increased until the refresh rate exceeds the effective frame rate of the content or until a maximum value is reached.

Abstract: One embodiment of the invention sets forth a mechanism for compiling a vertex shader program into two portions, a culling portion and a shading portion. The culling portion of the compiled vertex shader program specifies vertex attributes and instructions of the vertex shader program needed to determine whether early vertex culling operations should be performed on a batch of vertices associated with one or more primitives of a graphics scene. The shading portion of the compiled vertex shader program specifies the remaining vertex attributes and instructions of the vertex shader program for performing vertex lighting and performing other operations on the vertices in the batch of vertices. When the compiled vertex shader program is executed by graphics processing hardware, the shading portion of the compiled vertex shader is executed only when early vertex culling operations are not performed on the batch of vertices.

Abstract: A system, method, and computer program product are provided for hierarchical formal hardware verification of floating-point division and/or square root algorithmic designs using automatic sequential equivalence checking. In use, for at least one of a floating-point division algorithm and a square root algorithm, an architectural specification for hardware, a hardware implementation on the hardware, and at least one intermediate model having a level of specificity between the architectural specification and the hardware implementation are identified. Additionally, an equivalence is automatically determined, hierarchically, between the architectural specification, and the at least one intermediate model, and between the at least one intermediate model and the hardware implementation. Furthermore, for the hardware, the at least one of the floating-point division algorithm and the square root algorithm are formally verified, based on the automatic sequential equivalence determination.

Abstract: Embodiments related to fetching instructions and alternate versions achieving the same functionality as the instructions from an instruction cache included in a microprocessor are provided. In one example, a method is provided, comprising, at an example microprocessor, fetching an instruction from an instruction cache. The example method also includes hashing an address for the instruction to determine whether an alternate version of the instruction which achieves the same functionality as the instruction exists. The example method further includes, if hashing results in a determination that such an alternate version exists, aborting fetching of the instruction and retrieving and executing the alternate version.

Abstract: A circuit board includes a substrate and a conductive trace. An electronic element is electrically coupled with the conductive trace. A pair of holes pass through the substrate and are disposed respectively at two opposite sides of the conductive trace and adjacent to the conductive trace. A current-measuring device may be adapted for passing through the holes and surrounding the conductive trace.

Abstract: A method for estimating pixel intensity includes generating a plurality of bidirectional paths extending between a light source and a measurement point, whereby the measurement point represents a pixel within the image. Each bidirectional path includes a light subpath portion extending from the light source and an eye subpath portion extending from the view point and coupled to the light subpath. Each light subpath is characterized by a number of vertices included therein, and similarly, each eye subpath is characterized by a number of vertices included therein. The plurality of bidirectional paths are sorted into separation populations, whereby each population includes bidirectional paths constructed from eye subpaths having a common number of vertices, and light subpaths having a common number of vertices. An intensity contribution is computed for each of the individual populations, and the intensity contributions are summed over all populations to estimate the intensity of the pixel.

Abstract: A system, method, and computer program product are provided for determining an angle of polarization for a display device. Further, a polarization associated with shutter glasses is rotated the determined angle for viewing the display device utilizing the shutter glasses.

Abstract: A system, method, and computer program product are provided for validating an aspect of media data processing utilizing a signature. In use, media data is received in a system. Additionally, at least one signature of at least a portion of the media data is generated. Furthermore, at least one aspect of processing of the media data by the system is validated utilizing the at least one signature.

Abstract: One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread.

Abstract: One embodiment of the present invention sets forth a method for accessing, from within a graphics processing unit (GPU), data objects stored in a memory accessible by the GPU. The method comprises the steps of creating a data object in the memory based on a command received from an application program, transmitting an address associated with the data object to the application program for providing data associated with different draw commands to the GPU, receiving a first draw command and the address associated with the data object from the application program, and transmitting the first draw command and the address associated with the data object to the GPU for processing.

Abstract: One embodiment of the invention sets forth a method for toggling between video scanouts generated by a plurality of graphics processing units. The method includes the steps of transmitting a set of programming instructions to a first graphics processing unit and to a second graphics processing unit, configuring a first state machine within the first graphics processing unit to cause a trigger signal to be included with each video frame transmitted by the first graphics processing unit for display, and configuring a second state machine within the second graphics processing unit to cause a trigger signal to be included with each video frame transmitted by the second graphics processing unit for display. The method advantageously creates a direct relationship between the transmission frequencies of the individual graphics processing units and the switching frequency of a video bridge, not relying on a driver to control the video bridge switching.

Abstract: One embodiment of the present invention sets forth a technique for displaying high-resolution images using multiple graphics processing units (GPUs). The graphics driver is configured to present one virtual display device, simulating a high-resolution mosaic display surface, to the operating system and the application programs. The graphics driver is also configured to partition the display surface amongst the GPUs and transmit commands and data to the local memory associated with the first GPU. A video bridge automatically broadcasts this information to the local memories associated with the remaining GPUs. Each GPU renders and displays only the partition of the display surface assigned to that particular GPU, and the GPUs are synchronized to ensure the continuity of the displayed images. This technique allows the system to display higher resolution images than the system hardware would otherwise support, transparently to the operating system and the application programs.

Abstract: A system and method are provided for approximating a diffusion profile utilizing gathered lighting information associated with an occluded portion of an object. In use, the present technique gathers information associated with an occluded portion of an object that is illuminated with a two-dimensional pattern of light including an edge which defines an illuminated portion and the occluded portion of the object. To this end, a diffusion profile of the object is approximated, utilizing such information.

Abstract: One embodiment of the present invention sets forth a method for sharing graphics objects between a compute unified device architecture (CUDA) application programming interface (API) and a graphics API. The CUDA API includes calls used to alias graphics objects allocated by the graphics API and, subsequently, synchronize accesses to the graphics objects. When an application program emits a “register” call that targets a particular graphics object, the CUDA API ensures that the graphics object is in the device memory, and maps the graphics object into the CUDA address space. Subsequently, when the application program emits “map” and “unmap” calls, the CUDA API respectively enables and disables accesses to the graphics object through the CUDA API. Further, the CUDA API uses semaphores to synchronize accesses to the shared graphics object. Finally, when the application program emits an “unregister” call, the CUDA API configures the computing system to disregard interoperability constraints.