Abstract: Circuits, methods, and apparatus that reduce the amount of data read from an external memory by a processor when performing calculations on data sets such as matrices or lattices. In one example, a computation algorithm is executed by threads running on a parallel processor such as a single-instruction, multiple-data processor, which stores computational data in on chip memories. Data to be processed by a group of threads is read from the external memory and stored in a first on-chip memory, while a copy of data to be processed at a later time by the group of threads is stored in a second on-chip memory. Data in the first on-chip memory is processed multiple times before being written to the external memory. Processing data multiple times and keeping a copy of data for later use reduces the amount of data to be retrieved from memory, thereby improving computational efficiency.

Abstract: A method and system for deferred coverage mask generation in a raster stage of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and performing a bounding box test on the graphics primitive to define a bounding rectangle for the graphics primitive. A combined coverage mask is then generated after the completion of the bounding box test. The combined coverage mask indicates a plurality of pixels that are covered by the graphics primitive. The combined coverage mask is divided into a plurality of sub-portions. The sub-portions are allocated to a plurality of raster components to determine sub-pixel coverage for the sub-portions.

Abstract: A method and system for using bundle decoders in a processing pipeline is disclosed. In one embodiment, to perform a context switch between a first process and a second process operating in a processing pipeline, the first state information that is associated with the first process is placed on a connection separate from the processing pipeline. A number of decoders are coupled to this connection. The decoders obtain the first state information from a number of pipeline units on the processing pipeline by monitoring the data stream going into these pipeline units. Also, to restore the first state information after having switched out the second state information that is associated with the second process, the first state information is placed on the connection for the decoders to retrieve.

Abstract: The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled.

Abstract: A system and method for constructing binary radix trees in parallel, which are used for as a building block for constructing secondary trees. A non-transitory computer-readable storage medium having computer-executable instructions for causing a computer system to perform a method is disclosed. The method includes determining a plurality of primitives comprising a total number of primitive nodes that are indexed, wherein the plurality of primitives correspond to leaf nodes of a hierarchical tree. The method includes sorting the plurality of primitives. The method includes building the hierarchical tree in a manner requiring at most a linear amount of temporary storage with respect to the total number of primitive nodes. The method includes building an internal node of the hierarchical tree in parallel with one or more of its ancestor nodes.

Abstract: A non-transitory computer-readable storage medium having computer-executable instructions for causing a computer system to perform a method for constructing k-d trees, octrees, and quadtrees from radix trees is disclosed. The method includes assigning a Morton code for each of a plurality of primitives corresponding to leaf nodes of a binary radix tree, and sorting the plurality of Morton codes. The method includes building a radix tree requiring at most a linear amount of temporary storage with respect to the leaf nodes, wherein an internal node is built in parallel with one or more of its ancestor nodes. The method includes, partitioning the plurality of Morton codes for each node of the radix tree into categories based on a corresponding highest differing bit to build a k-d tree. A number of octree or quadtree nodes is determined for each node of the k-d tree. A total number of nodes in the octree or quadtree is determined, allocated and output.

Abstract: Embodiments of the present invention may be directed to an electronic connector. More specifically, the electronic connector may include a single connector body and a mounting end operable to couple the single connector body with an electronic board of an electronics unit. The electronic connector may also include a lower jack portion disposed in the single connector body and include multiple lower pin receptacles, where the lower jack portion is disposed adjacent to the mounting end and is operable to receive a first connector end of a first cable. The electronic connector may further include an upper jack portion disposed in the single connector body and include multiple upper pin receptacles, where the upper jack portion is disposed above the lower jack portion and is operable to receive a second connector end of a second cable.

Abstract: Method, receiver and computer program product for processing a signal transmitted from a plurality of spatially separated transmit antennas using a Multiple-Input Multiple-Output transmission over a wireless network. The signal is received at a plurality of spatially separated receive antennas, the signal comprising a plurality of data streams and the quality/reliability of each of the data streams in the received signal is determined. Based on the determined quality/reliability of the data streams, a decoding technique is selected to be one of (i) a successive decoding technique for successively decoding data streams in which one of the data streams is decoded and a signal corresponding to said one of the data streams is removed from the received signal prior to decoding further data streams in the received signal, and (ii) a non-successive decoding technique in which each data stream is decoded from the received signal by treating the other data streams as noise in the received signal.

Abstract: A non-transitory computer-readable storage medium having computer-executable instructions for causing a computer system to perform a method for constructing bounding volume hierarchies from binary trees is disclosed. The method includes providing a binary tree including a plurality of leaf nodes and a plurality of internal nodes. Each of the plurality of internal nodes is uniquely associated with two child nodes, wherein each child node comprises either an internal node or leaf node. The method also includes determining a plurality of bounding volumes for nodes in the binary tree by traversing the binary tree from the plurality of leaf nodes upwards toward a root node, wherein each parent node is processed once by a later arriving corresponding child node.

Abstract: A display refresh system, method and computer program product are provided. In use, at least one aspect of a display of content is identified by monitoring commands. Based on such identified aspect(s), a refresh rate of a display utilized for the display of the content may be adjusted.

Abstract: A system and method for communicating over a single virtual channel. The method includes reserving a first group of credits of a credit pool for a first traffic class and a second group of credits of the credit pool for a second traffic class. In addition, a first and second respective groups of tags are reserved from a tag pool for the first and second traffic class. A packet may then be selected from a first buffer for transmission over the virtual channel. The packet may include a traffic indicator of the first traffic class operable to allow the packet to pass a packet of the second traffic class from a second buffer. The method further includes sending the packet over the virtual channel and adjusting the first group of credits and the first group of tags based on having sent a packet of the first traffic class.

Abstract: A shared resource management system and method are described. In one embodiment, a shared resource management system facilitates age based miss replay. In one exemplary implementation, a shared resource management system includes a plurality of engines, and a shared resource a shared resource management unit. The plurality of engines perform processing. The shared resource supports the processing. The shared resource management unit handles multiple outstanding miss requests.

Abstract: One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.

Abstract: A system, method, and computer program product are provided for hierarchical formal hardware verification of floating-point division and/or square root algorithmic designs using automatic sequential equivalence checking. In use, for at least one of a floating-point division algorithm and a square root algorithm, an architectural specification for hardware, a hardware implementation on the hardware, and at least one intermediate model having a level of specificity between the architectural specification and the hardware implementation are identified. Additionally, an equivalence is automatically determined, hierarchically, between the architectural specification, and the at least one intermediate model, and between the at least one intermediate model and the hardware implementation. Furthermore, for the hardware, the at least one of the floating-point division algorithm and the square root algorithm are formally verified, based on the automatic sequential equivalence determination.

Abstract: A semaphore system, method, and computer program product are provided for use in a graphics environment. In operation, a semaphore is operated upon utilizing a plurality of graphics processing modules for a variety of graphics processing-related purposes (e.g. for example, controlling access to graphics data by the graphics processing modules, etc.).

Abstract: Method and apparatus for processing a signal using a recursive method for determining a plurality of frequency components of the signal, the signal being a chirp-like polyphase sequence, wherein a first frequency component of the plurality of frequency components is determined; a component factor is determined by accessing a factor table for use in determining a second frequency component of the plurality of frequency components; and the second frequency component is determined using the determined first frequency component and the determined component factor.

Abstract: An electronic device is configured to receive data from a keypad key, wherein the key is associated with first and second alphanumeric characters. The device includes a keypad interface and a data entry processor. The keypad interface is configured to determine the first and second alphanumeric characters when the key is pressed. The data entry processor is configured to select the first alphanumeric character from among the first and second alphanumeric characters when a speech recognizer determines that a spoken entry identifies the first alphanumeric character.

Abstract: Method, receiver and computer program product for processing a signal transmitted over a wireless network from a plurality of spatially separated transmit antennas of a transmitter using a Multiple-Input Multiple-Output transmission. The signal is received at a plurality of receive antennas, the signal comprising a plurality of data streams. The channel quality for each of the data streams in the received signal is determined and based on the determined channel quality of the data streams, the number of independent data streams that can be supported in the Multiple-Input Multiple-Output transmission of the signal is determined. An indication of the determined number is transmitted to the transmitter.

Abstract: A sound-activated control system includes an audio receiver and a command discriminator. The receiver is configured to receive an audio waveform and to produce a digital audio waveform therefrom. The command discriminator is configured to detect a temporally and/or spectrally compact nonphonetic audio command within the digital audio waveform and to control a voice-activated system an action in response to the nonphonetic command.

Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.