Patents Assigned to NVidia
  • Hardware override of application programming interface programmed state
    Patent number: 8493395
    Abstract: A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 23, 2013
    Assignee: Nvidia Corporation
    Inventors: Jerome F. Duluk, Jr., Henry P. Moreton, Steven E. Molnar, John S. Montrym
  • Partial coverage layers for color compression
    Patent number: 8488890
    Abstract: One embodiment of the present invention sets forth a technique for compressing image data with high contrast between pixels within a tile and between samples within pixels without any data loss. Partial coverage layers are generated and written to a tile that includes multiple pixels without reading the existing image data that is stored for the tile. A partial coverage layer encodes image data, such as colors, and sub-pixel coverage information for each covered pixel in a tile. The use of partial coverage layers reduces the bandwidth used to store image data when a tile is not fully covered.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: July 16, 2013
    Assignee: Nvidia Corporation
    Inventors: David Kirk McAllister, Narayan Kulshrestha, Steven E. Molnar
  • Hardware WCK2CK training engine using meta-EDC sweeping and adjustably accurate voting algorithm for clock phase detection
    Patent number: 8489911
    Abstract: One embodiment of the present invention sets forth a technique for performing high-performance clock training. One clock training sweep operation is performed to determine phase relationships for two write clocks with respect to a command clock. The phase relationships are generated to satisfy timing requirements for two different client devices, such as GDDR5 DRAM components. A second clock training sweep operation is performed to better align local clocks operating on the client devices. A voting tally is maintained during the second clock training sweep to record phase agreement at each step in the clock training sweep. The voting tally then determines whether one of the local clocks should be inverted to better align the two local clocks.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: July 16, 2013
    Assignee: NVIDIA Corporation
    Inventors: Eric Lyell Hill, Russell R. Newcomb, Shu-Yi Yu
  • Processing of read requests in a memory controller using pre-fetch mechanism
    Patent number: 8489851
    Abstract: A memory controller provided according to an aspect of the present invention includes a predictor block which predicts future read requests after converting the memory address in a prior read request received from the processor to an address space consistent with the implementation of a memory unit. According to another aspect of the present invention, the predicted requests are granted access to a memory unit only when there are no requests pending from processors and the peripherals sending access requests to the memory unit.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: July 16, 2013
    Assignee: NVIDIA Corporation
    Inventors: Balajee Vamanan, Tukaram Methar, Mrudula Kanuri, Sreenivas Krishnan
  • Method of verifying the performance model of an integrated circuit
    Patent number: 8489377
    Abstract: A method of verifying a performance model of an integrated circuit is provided. The method comprises the following steps: obtaining statistical request numbers and corresponding latency values of memory access requests; developing functions of latency value based on the statistical request numbers and the corresponding latency values; bringing a random value to one of the functions to retrieve a latency value; and verifying the logic of the performance model using the latency value retrieved in the step above.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: July 16, 2013
    Assignee: Nvidia Corporation
    Inventors: Reuel William Nash, Yu Bai, Xiaowei Li
  • Multimedia framework to provide ultra-low power multimedia playback
    Patent number: 8488951
    Abstract: A method of multimedia processing includes providing a multimedia processor operating at a frequency lower than that of a central processor of a multimedia processing system. A multimedia framework is implemented in the multimedia processing system. The multimedia framework is utilized to execute, on the multimedia processor, one or more of reading an input, transforming a data based on the reading of the input, and placing an output based on the transforming of the data on a rendering device. Power dissipated in the multimedia processing system is reduced by solely executing a requisite parsing on the central processor of the multimedia processing system.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: July 16, 2013
    Assignee: Nvidia Corporation
    Inventors: Mayuresh Kulkarni, Dhiraj Nadgouda
  • Dual-trigger low-energy flip-flop circuit
    Patent number: 8487681
    Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: July 16, 2013
    Assignee: NVIDIA Corporation
    Inventors: William J. Dally, Jonah M. Alben, John W. Poulton, G E (Francis) Yang
  • Increasing memory capacity of a frame buffer via a memory splitter chip
    Patent number: 8489839
    Abstract: The memory splitter chip couples multiple DRAM units to the PPU, thereby expanding the memory capacity available to the PPU for storing data and increasing the overall performance of the graphics processing system. The memory splitter chip includes logic for managing the transmission of data between the PPU and the DRAM units when the transmission frequencies and the burst lengths of the PPU interface and the DRAM interfaces differ. Specifically, the memory splitter chip implements an overlapping transmission mode, a pairing transmission mode or a combination of the two modes when the transmission frequencies or the burst lengths differ.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: July 16, 2013
    Assignee: Nvidia Corporation
    Inventors: Ashish Karandikar, Kaustubh Sanghani, Jonah M. Alben, Shane Keil
  • GRAPHICS PROCESSOR CLOCK SCALING BASED ON IDLE TIME
    Publication number: 20130179711
    Abstract: A method for graphics processor clock scaling comprises the following steps. A percentage of idle-time is calculated, based upon an elapsed idle-time and an elapsed active time. A graphics processor clock rate is reduced if the percentage of idle time is higher than a high limit threshold. The graphics processor clock rate is increased if the percentage of idle time is lower than a low limit threshold.
    Type: Application
    Filed: December 12, 2012
    Publication date: July 11, 2013
    Applicant: NVIDIA CORPORATION
    Inventor: NVIDIA Corporation
  • SMOOTH RASTERIZATION OF POLYGONAL GRAPHICS PRIMITIVES
    Publication number: 20130176330
    Abstract: A method and system for smooth rasterization of graphics primitives. The method includes receiving a graphics primitive for rasterization in a raster stage of a processor, rasterizing the graphics primitive by generating a plurality of fragments related to the graphics primitive, and determining a coverage value for each of the plurality of fragments. If one edge of the graphics primitive lies within a predetermined inter-pixel distance from a pixel center, the one edge is used to calculate the coverage value by using a distance to the pixel center. If two edges of the graphics primitive lie within the predetermined inter-pixel distance from the pixel center, a distance to the pixel center of each edge is used individually to calculate the coverage value. The resulting coverage values for the plurality of fragments are output to a subsequent stage of the processor for rendering.
    Type: Application
    Filed: August 7, 2012
    Publication date: July 11, 2013
    Applicant: NVIDIA CORPORATION
    Inventor: Franklin C. Crow
  • INSTRUCTION CACHE POWER REDUCTION
    Publication number: 20130179640
    Abstract: In one embodiment, a method for controlling an instruction cache including a least-recently-used bits array, a tag array, and a data array, includes looking up, in the least-recently-used bits array, least-recently-used bits for each of a plurality of cacheline sets in the instruction cache, determining a most-recently-used way in a designated cacheline set of the plurality of cacheline sets based on the least-recently-used bits for the designated cacheline, looking up, in the tag array, tags for one or more ways in the designated cacheline set, looking up, in the data array, data stored in the most-recently-used way in the designated cacheline set, and if there is a cache hit in the most-recently-used way, retrieving the data stored in the most-recently-used way from the data array.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 11, 2013
    Applicant: NVIDIA CORPORATION
    Inventors: Aneesh Aggarwal, Ross Segelken, Kevin Koschoreck
  • TOUCH-SCREEN INPUT/OUTPUT DEVICE TOUCH SENSING TECHNIQUES
    Publication number: 20130176251
    Abstract: A touch-screen input/output device including a touch sensor, a display, a display control module, a touch sensor control module and a synchronizer module. The touch sensor is overlaid on a display. The display control module is communicatively coupled to the display and converts video data into a serial bit stream video display signal include one or more blanking intervals. The touch sensor control module is communicatively coupled to the touch sensor and determines touch events and location of the touch event on the touch sensor during one or more touch sensor scan cycles. The synchronizer module is communicatively coupled between the display control module and the touch sensor control module, and interleaves the one or more touch sensor scan cycles with the one or more blanking intervals of the video display signal.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 11, 2013
    Applicant: NVIDIA CORPORATION
    Inventor: NVIDIA CORPORATION
  • Touch-Screen Input/Output Device Techniques
    Publication number: 20130176213
    Abstract: A state machine implemented method for operating a touch-screen input/output device includes determining charge levels from a touch sensor by scan logic. The charge levels from the touch sensor are converted to digital charge data by an analog-to-digital converter. Potential touch events and potential touch event location data is detected from the digital charge data by sensing logic. The potential touch events and potential touch event location data are compared to predetermined limits to determine touch events and locations that satisfy a predetermined level of accuracy by threshold management logic.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 11, 2013
    Applicant: NVIDIA CORPORATION
    Inventors: Arman Toorians, Ali Ekici, Robert Collins
  • Arrangement and method for radio network relocation
    Patent number: 8483687
    Abstract: An arrangement and method for radio network relocation of a mobile terminal (114) from a first base station controller (122) to a second base station controller (122?) by anchoring at least some SGSN functions with respect to the first base station controller; and relocating at least some RNC functions from the first base station controller to the second base station controller. RNC (124), SGSN (132) and GGSN (134) components may be integrated together, and the RNC (124) may be parented by an SGSN. Alternatively, RANAP SGSN functionality may be split between SGSN and RNC, RANAP and user plane signals may be relayed by the first base station controller to the second base station controller, and the first base station controller may act as an anchor.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: July 9, 2013
    Assignee: Nvidia Corporation
    Inventors: Andrew Gordon Williams, Timothy J. Speight
  • System, method, and computer program product for calculating statistics associated with a surface to be rendered utilizing a graphics processor
    Patent number: 8482574
    Abstract: A system, method, and computer program product are provided for calculating statistics associated with a surface to be rendered utilizing a graphics processor. In use, w-values are identified using a graphics processor. Additionally, the graphics processor is utilized for calculating statistics associated with at least one surface to be rendered using the w-values. Furthermore, the statistics are stored.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: July 9, 2013
    Assignee: NVIDIA Corporation
    Inventors: David Robert Cook, Jacob Markovich Kurlyandchik
  • Line rasterization techniques
    Patent number: 8482567
    Abstract: A line rasterization technique in accordance with one embodiment includes conditioning a line by pulling in the ending vertex of the line or pushing out the starting vertex of the line. Thereafter, if the line exits a diamond test area of each pixel that it touches, the pixel may be lit.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: July 9, 2013
    Assignee: Nvidia Corporation
    Inventors: Henry Packard Moreton, Franklin C. Crow
  • Combined heat sink multi-configuration processor memory substrate device
    Patent number: 8482120
    Abstract: A Multi-configuration Processor-Memory device for coupling to a PCB (printed circuit board) interface. The device comprises a substrate that supports multiple configurations of memory components and a processor while having a single, common interface with a PCB interface of a printed circuit board. In a first configuration, the substrate supports a processor and a first number of memory components. In a second configuration, the substrate supports a processor and an additional number of memory components. The memory components can be pre-tested, packaged memory components mounted on the substrate. The processor can be a surface mounted processor die. Additionally, the processor can be mounted in a flip chip configuration, side-opposite the memory components. In the first configuration, a heat spreader can be mounted on the memory components and the processor to dissipate heat.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: July 9, 2013
    Assignee: Nvidia Corporation
    Inventors: Behdad Jafari, George Sorensen
  • TEXTURE PIPELINE CONTEXT SWITCH
    Publication number: 20130169651
    Abstract: Circuits, methods, and apparatus that perform a context switch quickly while not wasting a significant amount of in-progress work. A texture pipeline includes a cutoff point or stage. After receipt of a context switch instruction, texture requests and state updates above the cutoff point are stored in a memory, while those below the cutoff point are processed before the context switch is completed. After this processing is complete, global states in the texture pipeline are stored in the memory. A previous context may then be restored by reading its texture requests and global states from the memory and loading them into the texture pipeline. The location of the cutoff point can be a point in the pipeline where a texture request can no longer result in a page fault in the memory.
    Type: Application
    Filed: February 25, 2013
    Publication date: July 4, 2013
    Applicant: NVIDIA Corporation
    Inventor: NVIDIA Corporation
  • OPPORTUNISTIC FRAME BUFFER COPY FOR EFFICIENT MEMORY PARTIAL POWER DOWN
    Publication number: 20130169656
    Abstract: Embodiments of the present invention may be directed to a graphics system of a computer system. The system may include a frame buffer having a number of partitions respectively mapped to a number of discrete memory devices and a dedicated copy buffer operable to store new image frames, mapped to a first memory device. The first memory device corresponds to a first partition of the number of partitions. The system may also include a loader circuit coupled between the frame buffer and the dedicated copy buffer, operable to copy new image frames from the frame buffer to the dedicated copy buffer. The system may also include a clocked output coupled to receive an image frame from the dedicated copy buffer and operable to drive a display device therewith. The system may enter a low power state wherein a number of the discrete memory devices are powered off.
    Type: Application
    Filed: May 18, 2012
    Publication date: July 4, 2013
    Applicant: NVIDIA CORPORATION
    Inventors: Christopher Thomas Cheng, Sau Yan Keith Li, Thomas Edward Dewey, Franciscus W. Sijstermans
  • Method and system for protecting content in graphics memory
    Patent number: 8478959
    Abstract: A method and system for protecting content in graphics memory are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of storing a first privilege level in a privilege map with restricted access, wherein the first privilege level is associated with a memory page used to store the content; and determining whether to permit a request to access the memory page based on the first privilege level.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: July 2, 2013
    Assignee: NVIDIA Corporation
    Inventor: David Wyatt