Abstract: A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment.

Abstract: A clock gating mechanism controls power within an integrated circuit device. One or more clock gating circuits are configured to couple a system clock to a different portion of the integrated circuit device. A logic circuit applies an enabling signal to one of the clock gating circuits to control whether the system clock passes through the clock gating circuit to a portion of the integrated circuit device associated with the clock gating circuit. A plurality of scan flip-flops is configured to provide a binary code to the logic circuit, where the binary code indicates to the logic circuit that the enabling signal should be applied to the clock gating circuit. One advantage of the disclosed technique is that power droop during at-speed testing of a device is reduced without significantly increasing the quantity of test vectors or reducing test coverage, resulting in greater test yields and lower test times.

Abstract: An arithmetic logic stage in a graphics pipeline includes a number of arithmetic logic units (ALUs). The ALUs each include, for example, a multiplier and an adder. The ALUs are interconnected by circuitry that, for example, routes the output from the multiplier in one ALU to both the adder in that ALU and an adder in another ALU.

Abstract: Video filtering using a programmable graphics processor is described. The programmable graphics processor may be programmed to complete a plurality of video filtering operations in a single pass through a fragment-processing pipeline within the programmable graphics processor. Video filtering functions such as deinterlacing, chroma up-sampling, scaling, and deblocking may be performed by the fragment-processing pipeline. The fragment-processing pipeline may be programmed to perform motion adaptive deinterlacing, wherein a spatially variant filter determines, on a pixel basis, whether a “bob”, a “blend”, or a “weave” operation should be used to process an interlaced image.

Abstract: A system and method are provided for determining a time for safely sampling a signal of a dock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first dock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.

Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. The output signal Q is set or reset at the rising clock edge using a single-trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract: A method for controlling data transmission from a machine-type communication (MTC) entity over a radio network in a wireless telecommunications system is described. The method comprises receiving from the radio network a transmission cost parameter representing a cost associated with transmitting data over the radio network; and controlling data transmission from the MTC entity in dependence on the transmission cost parameter. Thus the MTC entity is able to select times and/or manner of data transmissions to reduce the overall cost of using the network. Furthermore, the radio network is able to dynamically manage traffic load by providing a cost incentive for transmitting MTC data when network resources are under utilised and applying a cost penalty for transmissions made while the network is relatively busy.

Abstract: An Orthogonal Frequency Division Multiplex (OFDM) communication system comprises OFDM transmitters and an OFDM receiver. The system comprises a subcarrier status data controller for transmitting subcarrier status data to the OFDM receiver. The subcarrier status data indicates the active subcarriers of the OFDM transmitters. The OFDM receiver comprises a receiver which receives a signal comprising a desired signal component from a first OFDM transmitter and interference from at least one interfering OFDM transmitter. The OFDM receiver further comprises a subcarrier status processor which receives the subcarrier status data and a channel estimator which determines channel estimates for at least an air interface communication channel from the first OFDM transmitter and an air interface communication channel from the interfering OFDM transmitter. An interference mitigation processor performs interference mitigation of the interference in response to the subcarrier status data and the channel estimates.

Abstract: Systems and methods for using RAID with ATA mass storage devices can benefit from operating system optimizations for avoiding unaligned write accesses. When the ATA mass storage devices in the RAID array have different physical sector sizes, the largest physical sector size is reported as the physical sector size for the single disk represented by the RAID array. The operating system can optimize accesses that are aligned with all of the physical sector sizes within the RAID array. Additionally, any storage devices that have a first logical sector that does not have an offset of zero, are configured to ignore all logical sectors in the first physical sector. Accesses to the first logical sector are mapped to the second physical sector. A logical sector alignment of zero is then reported to the operating system for the RAID array, enabling the operating system to avoid unaligned writes.

Abstract: A computer system that employs Peripheral Component Interconnect Express (PCIe) links includes devices that generate a PCIe packet having a header portion that is smaller than the header portion for a conventional PCI packet. The devices may be an endpoint device, such as a graphics processor, and a chipset, such as a root-complex. The reduced size header improves the bus throughput efficiency of the computer system and reduces power requirements for the computer system.

Abstract: A system, method, and computer program product are provided for calculating adjustments for images. In use, a plurality of images is identified. Additionally, one or more discrepancies are determined between the plurality of images. Further, one or more adjustments are calculated for one or more of the plurality of images, utilizing the determined one or more discrepancies.

Abstract: A system, method, and computer program product are provided for evaluating an integral utilizing a low discrepancy sequence and a block size. In use, a low discrepancy sequence and a block size are determined. Additionally, an integral is evaluated, utilizing the low discrepancy sequence and the block size.

Abstract: A central processing unit (CPU) can specify an initial (e.g., baseline) frequency for a clock signal used by a device to perform a task. The CPU is then placed in a reduced power mode. The device performs the task after the CPU is placed in the reduced power mode until a triggering event causes the device to send an interrupt to the CPU. In response to the interrupt, the CPU awakens to dynamically adjust the clock frequency. If the clock frequency is reset to the baseline value, then the CPU is again placed in the reduced power mode.

Abstract: A method of RAID migration comprising reading first and second blocks from a first RAID array. Said first blocks are written to a second RAID array within a first write cycle. Said second blocks are read simultaneously with a portion of said first write cycle in a pipelined fashion. In a first embodiment, pipelining increases the speed of RAID migration from a one-disk stripe array to a two-disk mirror array. In a second embodiment, pipelining and the use of duplicate blocks increases the speed of RAID migration from a two-disk mirror array to a three-disk RAID 5 array. In a third embodiment, pipelining and the use of duplicate blocks increases the speed of RAID migration from a three-disk RAID 5 array to a four-disk RAID 5 array.

Abstract: A method, system and an apparatus of resonant induction to power a graphics processing unit (GPU) are disclosed. In one embodiment, a resonant induction system is described. The resonant induction system includes a transmitter circuit tuned to a resonant frequency. The transmitter circuit generates a non-radiative magnetic field when a control current is passed through the transmitter circuit. The resonant induction system also includes a receiver circuit, resonantly coupled to the non-radiative magnetic field generated by the transmitter circuit, and tuned to the resonant frequency of the transmitter circuit. The receiver circuit is located in a GPU. The transmitter circuit and the receiver circuit are resonantly coupled to each other at the resonant frequency. A control current source supplies the control current to the transmitter circuit. A feedback module may be communicatively coupled to the GPU to determine a power requirement of a particular computer graphics application.

Abstract: A scalable scan-based architecture with reduced test time, test power and test pin-count in scan based testing of ICs. In an embodiment, a test vector is scanned serially into a functional memory element at a first frequency, which then de-multiplexes the bits in the test vector to multiple sub-chains at a lower frequency. Due to the use of lower frequency to scan-in, the power dissipation is reduced. Due to the use of the higher frequency to scan-in the test vector as well as multiple sub-chains, the test time is reduced. Due to the use of the functional memory elements for scanning in the test vector at higher frequency, any number of chains can potentially be supported.

Abstract: A method, system and apparatus for expandable housing of a mobile communication device are disclosed. A housing of a mobile communication device includes a base layer, at least one of a component layer coupled communicatively on either side of the base layer to enable modification of a modular peripheral component integrated into the housing by sliding the modular peripheral component through a set of grooves located on opposite sides of each of the component layer and the base layer and a holding mechanism in the component layer that enables the modular peripheral component to remain in a fixed position. The modular peripheral component includes a daisy-chainable expansion port that enables an additional modular peripheral component integratable in the mobile communication device to be communicatively coupled with the housing across a variety of physical connections of the daisy-chainable expansion port.

Abstract: A method, apparatus, and system of luminous power control of a light source of a multimedia processing system are disclosed. In one embodiment, a method is described. The method includes capturing a digital image of a face of a user. The method also includes applying, with a processor, an algorithm capable of detecting a digital facial feature of the face of the user based on one or more markers of the digital image. In addition, the method includes determining whether the digital image includes the digital facial feature according to the marker. The method further includes causing a light source to illuminate an electronic display at an active-mode luminous power level that includes a luminous power level different than a power-saving mode luminous power level of the light source when the digital image includes the digital facial feature.

Abstract: A method and system for selective enablement of tile compression. The method includes receiving a graphics primitive for processing in a set-up unit of a graphics processor and determining a primitive characteristic that indicates a probability of whether a final compression of a tile related to the primitive will be retained. Compression for the tile related to the primitive is allowed when the characteristic indicates the final compression will be retained. Compression for the tile related to the primitive is disallowed in the characteristic indicates the final compression will not be retained.

Abstract: A system, method, and computer program product are provided for adjusting a lens polarization. In use, one or more characteristics associated with a display are identified. Additionally, a polarization of one or more lenses is adjusted, based on the one or more characteristics.