Abstract: A chip comprising a signal transmitting circuit, a communication system between multiple chips and a method for configuring the communication system between multiple chips are provided. The signal transmitting circuit of the chip comprises a multi-route selector, a first bias resistor and a second bias resistor, a first signal line and a second signal line, and a signal transmitting end; wherein the multi-route selector comprises a first input end, a second input end, a selection input end and an output end, wherein the first input end is grounded, the second input end is connected to a DC bias voltage and the selection input end receives a selection signal; wherein the multi-route selector selects the first input end when the selection signal is a first selection signal, and the multi-route selector selects the second input end when the selection signal is a second selection signal.

Abstract: A wireless access network system comprises a RADIUS (Remote Access Dial-In User System) arrangement with an associated RADIUS accounting function. The RADIUS arrangement is arranged to track access activity by a user accessing the network via wireless user equipment and via the RADIUS arrangement. The access activity is recorded in an accounting database which is associated with the RADIUS accounting function. The wireless access system also comprises a radio network controller which comprises a RADIUS client. The RADIUS arrangement is arranged to receive information from a radio network controller of the system in order to track the access activity. The Invention is applicable to cellular communication systems such as UMTS (Universal Mobile Telecommunication System).

Abstract: A method and system for generating shadows for a graphics processing unit. Specifically, the method determines whether a potential blocker occludes light from reaching a point of a scene in an image space. The light is generated from a light source. A width of a corresponding penumbra is determined for the point. The width is based on a width of the light source, a depth of the potential blocker from the light source, and a depth of a receiver from the light source. The receiver includes the point. A percentage closer filtering kernel size is scaled in proportion to the width of the corresponding penumbra. Thereafter, percentage closer filtering is performed for the point using the kernel size that is scaled in order to shade a pixel corresponding to the point.

Abstract: Embodiments of the present invention provide for initializing a device for use in a computer system. In one embodiment a BIOS routine reads a configuration register of each device in a computer system. The configuration register contains a device identifier indicating an oldest version of a device driver for controlling the device. The device identifier for each device is saved in a configuration data space. An operating system retrieves each device identifier contained in the configuration data space, and maps each device identifier to a corresponding device driver utilizing a registry. The operating system loads and causes execution of an initialization routine of each corresponding device driver mapped to each of the device identifiers.

Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.

Abstract: Embodiments of the present invention include a computer-controlled method for safely operating a vehicle based electronic system. The method includes receiving a first signal from a first sensor, wherein the first sensor is for identifying the presence of a passenger located in a passenger seat of the vehicle. This may be the configuration of a seat belt associated with the passenger seat. The method further includes receiving a second signal from a second sensor, wherein the second sensor is for determining a weight of the passenger in the passenger seat. Provided the passenger is located in the passenger seat and the weight of the passenger in the passenger seat is above or equal to a threshold value, the method further includes allowing programming functionality of the electronic system while the vehicle is in motion. In one embodiment, the electronic system is a vehicle based navigation system.

Abstract: Described is a device (e.g., a cell phone incorporating a digital camera) that incorporates a graphics processing unit (GPU) to process image data in order to increase the quality of a rendered image. The processing power provided by a GPU means that, for example, an unacceptable pixel value (e.g., a pixel value associated with a malfunctioning or dead detector element) can be identified and replaced with a new value that is determined by averaging other pixel values. Also, for example, the device can be calibrated against benchmark data to generate correction factors for each detector element. The correction factors can be applied to the image data on a per-pixel basis. If the device is also adapted to record and/or play digital audio files, the audio performance of the device can be calibrated to determine correction factors for a range of audio frequencies.

Abstract: One embodiment of the present invention sets forth a technique for computing virtual addresses for accessing thread data. Components of the complete virtual address for a thread group are used to determine whether or not a cache line corresponding to the complete virtual address is not allocated in the cache. Actual computation of the complete virtual address is deferred until after determining that a cache line corresponding to the complete virtual address is not allocated in the cache.

Abstract: Described is a device (e.g., a cell phone incorporating a digital camera) that incorporates a graphics processing unit (GPU) to process image data in order to increase the quality of a rendered image. The processing power provided by a GPU means that, for example, an unacceptable pixel value (e.g., a pixel value associated with a malfunctioning or dead detector element) can be identified and replaced with a new value that is determined by averaging other pixel values. Also, for example, the device can be calibrated against benchmark data to generate correction factors for each detector element. The correction factors can be applied to the image data on a per-pixel basis. If the device is also adapted to record and/or play digital audio files, the audio performance of the device can be calibrated to determine correction factors for a range of audio frequencies.

Abstract: A method and system for supporting multiple display interface standards are disclosed. Specifically, one embodiment of the present invention sets forth a computing device, which includes a processing unit and a display interface. The display interface further includes a formatting logic and a set of output pins, wherein the formatting logic is configured to derive a first set of output signals conforming to a first display interface standard from a data stream, drive the first set of output signals via a set of output pins to a first display device supporting the first display interface standard, support a second display interface standard instead of the first display interface standard in response to a state change and derive the first set of output signals conforming to the second display interface standard, and drive the first set of output signals via the same set of output pins to a second display device supporting the second display interface standard.

Abstract: Described is a device (e.g., a cell phone incorporating a digital camera) that incorporates a graphics processing unit (GPU) to process image data in order to increase the quality of a rendered image. The processing power provided by a GPU means that, for example, an unacceptable pixel value (e.g., a pixel value associated with a malfunctioning or dead detector element) can be identified and replaced with a new value that is determined by averaging other pixel values. Also, for example, the device can be calibrated against benchmark data to generate correction factors for each detector element. The correction factors can be applied to the image data on a per-pixel basis. If the device is also adapted to record and/or play digital audio files, the audio performance of the device can be calibrated to determine correction factors for a range of audio frequencies.

Abstract: An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.

Abstract: A method of simulation comprises controlling an avatar in an environment. Movement of graphical elements is simulated in a fluid coordinate frame surrounding said avatar, wherein said graphical elements in said fluid coordinate frame obey a first rule set. Said graphical elements and a first region surrounding said fluid coordinate frame are animated, wherein said graphical elements in said first region obey a second rule set. Said fluid coordinate frame moves in response to said controlling of said avatar. In an embodiment, a blending region blends the movement of graphical elements inside the fluid coordinate frame and outside the fluid coordinate frame.

Abstract: A method of receiving data. A plurality of data signals and clocking signals are received over a source synchronous communication channel. The plurality of data signals is strobed with the clocking signal at a plurality of coarse time offset delays (e.g., time offset delays spanning over a data bit period). The plurality of error rates associated with the strobing at the plurality of coarse time offset delays is determined. Strobing design of a transmitting component (e.g., edge-strobed, center-strobed, etc.) may be determined based on the plurality of error rates. The error rates of the plurality of data signals strobed with a plurality of time offset delays close to the determined strobing design of the transmitting component is calculated. A time offset delay is selected based on the error rates. The plurality of data signals can be strobed with the selected time offset delay to recover the transmitted data signals.

Abstract: A display refresh system, method and computer program product are provided. In use, at least one aspect of a display of content is identified by monitoring commands. Based on such identified aspect(s), a refresh rate of a display utilized for the display of the content may be adjusted.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for author verification and authorization of object code. In one embodiment, program object code is linked with a plurality of data blocks to create linked object code and a MAP file. Thereafter, author verification is performed by executing a plurality of comparisons between the linked object code and the MAP file. In another embodiment, a digital signing procedure is performed on linked object code by creating a signature data block. The signature data block is then encrypted and written to the linked object code to create digitally-signed object code. In another embodiment, an application program embodied in linked object code generates a data packet. The data packet is then compared to a previously-generated signature data packet from the linked object code to determine if the linked object code is authorized.

Abstract: A system, method, and computer program product are provided for assigning elements of a matrix to processing threads. In use, a matrix is received to be processed by a parallel processing architecture. Such parallel processing architecture includes a plurality of processors each capable of processing a plurality of threads. Elements of the matrix are assigned to each of the threads for processing, utilizing an algorithm that increases a contiguousness of the elements being processed by each thread.

Abstract: A clock module is coupled in parallel to a number of data processing modules that are coupled in series. The data processing modules can be individually clock-gated. Each of the data processing modules can determine whether or not it can be placed into an idle state. To reduce power consumption, any subset of the data processing modules that are eligible to be placed in an idle state can be clock-gated. The remaining data processing modules can continue to receive clock signals from the clock module and thus can continue to process data.

Abstract: A method of displaying an image includes generating a contract in the display engine, transferring the contract to the memory controller before the end of a sweep, generating a contract amendment in response to changes in the display engine, transferring the contract amendment to the memory controller, making a decision whether the contract amendment can be processed, fetching data from the memory controller according to the contract incorporating the contract amendment if the decision is that the contract amendment can be processed, sending the fetched data to the display engine in an isochronous stream; and processing the fetched data using the display engine.

Abstract: A DGS (discrete graphics system) unit is disclosed. The DGS unit includes a system chassis configured to house a GPU, the GPU for executing 3-D graphics instructions, and a GPU mounting unit coupled to the system chassis and configured to receive the GPU. A serial bus connector is coupled to the chassis and is coupled to the GPU mounting unit, wherein the serial bus connector is configured removably connect the GPU to a computer system to enable the GPU to access the computer system via the serial bus connector and execute the 3-D graphics instructions for the computer system. A power supply coupled to the system chassis for supplying power to the GPU independent of the computer system.