Abstract: Described herein are embodiments for decoding and displaying video data. Several of these embodiments utilize a unified frame buffer management system, to facilitate better memory management in decoding and displaying compressed video. One approach describes a method of decoding and displaying compressed video data. The method involves receiving a compressed video frame, and allocating a frame buffer for use in decoding the compressed video frame. A frame identifier is assigned to the allocated frame buffer. The compressed video frame is decoded into the frame buffer, and the frame identifier is passed to a display module.

Abstract: A method for constructing a motion-compensated composite image of a scene includes acquiring a plurality of images of a scene over time, the plurality of images including an earlier-acquired image of the scene and a later-acquired image scene. The relative motion between the earlier and later acquired images are estimated, and an exposure parameter is computed based upon the estimated relative motion occurring between the earlier and later acquired images. A new image of the scene is acquired using the computed exposure parameter, and the earlier, later, and newly acquired images are combined to produce a motion-compensated composite image of the scene.

Abstract: In a raster stage of a graphics processor, a method for using low precision evaluation and high precision evaluation for conservative triage of polygon status. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive to generate a plurality of tiles of pixels related to the graphics primitive. The tiles are rasterized at a first level precision to generate a plurality of sub-tiles related to the graphics primitive, wherein the sub-tiles are evaluated against the graphics primitive at each of their respective corners. Each of the sub-tiles not related to the graphics primitive are discarded. The sub-tiles related to the graphics primitive are rasterized at a second level precision.

Abstract: A system, method, and computer program product are provided for performing operations on data utilizing a computation module. In use, input data is received at a computation module, utilizing a chassis removably coupled to the computation module. Additionally, one or more operations are performed on the data, utilizing the computation module. Further, output data is provided from the computation module, utilizing the chassis.

Abstract: A system and method for using command buffers as timeslices or periods of execution for a long running compute task on a graphics processor. Embodiments of the present invention allow execution of long running compute applications with operating systems that manage and schedule graphics processing unit (GPU) resources and that may have a predetermined execution time limit for each command buffer. The method includes receiving a request from an application and determining a plurality of command buffers required to execute the request. Each of the plurality of command buffers may correspond to some portion of execution time or timeslice. The method further includes sending the plurality of command buffers to an operating system operable for scheduling the plurality of command buffers for execution on a graphics processor. The command buffers from a different request are time multiplexed within the execution of the plurality of command buffers on the graphics processor.

Abstract: A system and method for constructing a bounding volume hierarchical structure are disclosed. The method includes defining a parent node for the bounding volume hierarchical structure, the parent node including a parent node bounding volume enclosing a plurality of objects. A first cost is computed for performing an object partition of the parent node bounding volume to produce a first plurality of child node bounding volumes, and a second cost is also computed for performing a spatial partitioning of the parent node bounding volume to produce a second plurality of child node bounding volumes. The bounding volume hierarchical structure is constructed employing the second plurality of child node bounding volumes produced from the spatial partitioning of the parent node bounding volume if the second cost is lower than the first cost.

Abstract: A method for performing node traversal operations of a treelet-composed hierarchical structure includes allocating a queue for each of the plurality of treelets, each queue operable to store ray-states entering a respective one of the treelets. The method additionally includes determining that a ray-state exits a first treelet of the hierarchical structure and enters a second treelet of the hierarchical structure. The method further includes forwarding the ray-state entering the second treelet to a processing element for processing therein, wherein the queue allocated to store ray-states entering the second treelet is bypassed.

Abstract: A bridge is disclosed having a security engine to protect digital content at insecure interfaces of the bridge. The bridge permits cryptographic services to he offloaded from a central processing unit to the bridge. The bridge receives a clear text input from a central processing unit. The bridge encrypts the clear text input as cipher text for storage in a memory. The bridge provided the cipher text to a graphics processing unit.

Abstract: A method and system for performing adaptive tessellation of a subdivision surface. The method includes the step of accessing a model of a surface for subdivision processing. The model is converted to an intermediate form to facilitate subdivision processing. The intermediate form of the model is then tessellated.

Abstract: A system, method, and computer program product are provided for transmitting wireless signals to one or more portable devices. In use, a plurality or wireless signals is received utilizing a plurality of protocols. In addition, the plurality of protocols associated with the plurality of wireless signals are converted to a single different protocol. Further, the plurality of wireless signals is transmitted to at least one portable device utilizing the single different protocol.

Abstract: One embodiment of the present invention sets forth a technique for synchronizing the execution of multiple cooperative thread arrays (CTAs) implementing a parallel algorithm that is mapped onto a graphics processing unit. An array of semaphores provides synchronization status to each CTA, while one designated thread within each CTA provides updated status for the CTA. The designated thread within each participating CTA reports completion of a given computational phase by updating a current semaphore within the array of semaphores. The designated thread then polls the status of the current semaphore until all participating CTAs have reported completion of the current computational phase. After each CTA has completed the current computational phase, all participating CTAs may proceed to the next computational phase.

Abstract: A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.

Abstract: A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.

Abstract: A digital video display response time compensation system and method are presented. A digital video display response time compensation system and method are utilized to direct adjustments in a display presentation. A test pattern response time compensation value determination process for establishing appropriate adjustment levels for a display is performed. A test pattern is displayed; user input on compensation to the test pattern display is received; pixel value calibration settings are determined based upon the user input; and the test pattern display appearance is altered based upon the pixel value calibration settings. After the appropriate pixel illumination adjustment values are establish a pixel value is received. The pixel value is adjusted in accordance with the response time compensation value and a response time compensated pixel value is output.

Abstract: A method of executing a physics simulation is performed in a system comprising a computational platform, a main application stored in the computational platform, a secondary application stored in the computational platform, and a cloth application programming interface (API) implemented in the computational platform. The method defines a cloth simulation call in the cloth API, and by operation of the main application, invokes a software routine using the cloth simulation call. Additionally, by operation of the secondary application, a state of the physics simulation is updated in response to the software routine.

Abstract: A system and method for calibration of serial links using serial-to-parallel loopback. Embodiments of the present invention are operable for calibrating serial links using parallel links thereby reducing the number of links that need calibration. The method includes sending serialized data over a serial interface and receiving parallel data via a parallel interface. The serialized data is looped back via the parallel interface. The method further includes comparing the parallel data and the serialized data for a match thereof and calibrating the serial interface by adjusting the sending of the serialized data until the comparing detects the match. The adjusting of the sending is operable to calibrate the sending of the serialized data over the serial interface.

Abstract: Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks according to a uniform clock grid throughout an ASIC of a non-uniform arrangement of non-uniformly sized logic partitions. According to one embodiment, clock sources and sinks are mapped to grid point locations and a novel grid routing process is performed to link them together. A clock routing macro is assigned to a corresponding partition and associated with the corresponding partition or logic unit according to a partition hierarchy. The underlying routing structure and resources of a clock routing macro are automatically renamed to correspond to the local partition in a script or schedule of programmed instructions, or a routing map. The position of blockages within a partition may also be detected and alternate routes for traversing the blockage may be preemptively determined as well.

Abstract: A system, method, and computer program product are provided for controlling at least one aspect of a graphics hardware processor, in response to a command that is prompted by a vocal utterance.

Abstract: Systems and methods are disclosed for managing the number of affirmatively associated cache lines related to the different sets of a data cache unit. A tag look-up unit implements two thresholds, which may be configurable thresholds, to manage the number of cache lines related to a given set that store dirty data or are reserved for in-flight read requests. If the number of affirmatively associated cache lines in a given set is equal to a maximum threshold, the tag look-up unit stalls future requests that require an available cache line within that set to be affirmatively associated. To reduce the number of stalled requests, the tag look-up unit transmits a high priority clean notification to a frame buffer logic when the number of affirmatively associated cache lines in a given set approaches the maximum threshold. The frame buffer logic then processes requests associated with that set preemptively.

Abstract: According to an aspect of the present invention, one of multiple clock signals of different relative phases is selected based on a desired delay magnitude, and the digital values received on an input signal are then synchronized to an edge (“first edge”) of the selected clock signal to provide the digital values with the desired delay magnitude. In an embodiment, the selected clock signal can be delayed by a fine value (less than the minimum phase difference of the multiple clock signals) to provide a wide span of desired delays. An aspect of the invention provides for a synchronization circuit with reduced latency and which is substantially invariant to process, voltage and temperature (PVT) changes.