Abstract: Described are method and systems that implement time frequency domain threshold interference and localization fusion to resolve interference issues in an automotive radar system, that produces spectrograms using Short-Time Fourier Transform (STFT) for all receiving antennas of the automotive radar system. For each STFT frequency a suppression threshold is determined. Interference is isolated for each STFT frequency by removing the interference from samples that are above the suppression threshold by using a filter. Direction of Arrival (DoA) is estimated for each interference spectrogram cell using measurements from all the receiving antennas. Interference samples are clustered using the DoA into epochs of chirps.

Abstract: Aspects of the disclosure are directed to allocating bandwidth. As may be implemented in accordance with one or more embodiments, respective amounts of bandwidth are allocated to respective application groups for each memory access cycle in a set of memory access cycles. Initial bonus bandwidth is provided to a first one of the application groups during one of the memory access cycles. The bonus bandwidth may include at least a portion of bandwidth allocated to and unused by one of the other respective application groups during the memory access cycle. Additional bonus bandwidth is selectively provided to the first application group during one of the memory access cycles based on the initial bonus bandwidth and a maximum amount of bonus bandwidth defined for the set of memory access cycles, in response to bandwidth allocated to one of the other respective application groups during the subsequent memory access cycle being unused.

Abstract: Embodiments of multi-mode sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a multi-mode sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a controller configured to switch the multi-mode sigma-delta ADC circuit between a single-ended operational mode, a pseudo differential operational mode, and a full differential operational mode to improve common mode rejection (CMR) performance by controlling the pair of OTAs. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.

Abstract: A semiconductor package comprises a leadframe, a component module, and a semiconductor die. The leadframe has a plurality of insertion terminals, a split die pad, and one or more leads. The component module has one or more passive components mounted on a substrate. The semiconductor die has an integrated circuit. The component module is mounted on a split die pad at a first surface of the leadframe and forms an electrical connection with the insertion terminals. Further, the semiconductor die is mounted on the split die pad at a second surface of the leadframe which is opposite to the first surface.

Abstract: An integrated circuit (IC) includes first and second secure memory elements storing identical data and a memory management system that executes a memory operation on the first secure memory element and a control operation on the second secure memory element simultaneously. The control operation is associated with safety of the IC and is executed to enable error detection in the second secure memory element, fault injection for the second secure memory element, masking of a power profile associated with the memory operation, or a combination thereof. After the execution of the memory operation and the control operation, the memory management system copies the data of the first secure memory element to the second secure memory element to maintain sanity of the second secure memory element.

Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal. Hereby, the digital inputs provided to the DACs are non-randomized.

Abstract: A system-on-chip (SoC) having a switchable power domain capable of being placed in a standby mode during which a power supply of the switchable power domain is gated and having an always-on power domain. The always-on power domain includes an input sampling circuit, and the switchable power domain includes an input/output (IO) circuit configured to, during normal operation, receive data at a corresponding signal pin when an input buffer of the IO circuit is enabled, in which the corresponding signal pin is coupled to the input sampling circuit. The input sampling circuit is configured to, while the switchable power domain is entering the standby mode but before the power supply is gated, provide an override input enable signal to enable the input buffer of the IO circuit, sample an input bit value on the corresponding signal pin, and store the sampled bit value to provide an injection current fault indicator.

Abstract: Various embodiments relate to a multi-link device (MLD) access point configured to establish a target wake time (TWT) with a MLD station, wherein a plurality of links are established between the MLD access point and the MLD station, including: a transmitter configured to: transmit a TWT set up frame to the MLD station configured to indicate whether the TWT set up frame is applied to multiple links of the plurality of links; announce a broadcast TWT by transmitting a TWT element with just one Broadcast TWT Parameter Set field if a Broadcast TWT Parameter Set field includes optional fields; and negotiate with the MLD station an individual TWT for multiple links, through one TWT element wherein the number of the multiple links to which the individual TWTs applies is less than or equal than the number of radios of the MLD access point and the MLD station, and the number of the multiple links to which the individual TWTs applies is up to the total number of links when the MLD station is in eMLSR/eMLMR mode.

Abstract: A memory controller includes a transaction scheduler circuit and a command queue. For each access request received by the memory controller, the transaction scheduler circuit is configured to allocate a new entry in a scheduler queue, store an access address corresponding to the access request as a data address into the new entry, generate an error correction code (ECC) address from the data address and store the ECC address into the new entry, and set a corresponding ECC mode field in the new entry to indicate whether the data address or ECC address of the new entry is to be exposed during arbitration. The transaction scheduler circuit, during an arbitration cycle, is configured to select a transaction from the scheduler queue using an exposed address of each valid entry, and is configured to provide the selected transaction to the command queue.

Abstract: A System on Chip (SoC) includes a first core coupled to an interconnect; a second core coupled to the interconnect; a memory coupled to the interconnect and including a plurality of evenly sized partitions; and storage circuitry configured to store memory configuration information. The memory configuration information defines a memory configuration and is configured to indicate a series of swappable segments for each core of the SoC by indicating, for each core, a first number of partitions of the memory assigned to each of a first swappable segment and a second swappable segment for the core, the first swappable segment designated as an active segment and the second swappable segment designated as a first backup segment, and an enable indicator to indicate whether or not to assign the first number of partitions to a third swappable segment designated as a second backup segment.

Abstract: Aspects of the present disclosure are directed to radar and radar processing. As may be implemented in accordance with one or more embodiments involving multi-input multi-output (MIMO) co-prime radar signals transmitted by a plurality of transmitters and reflected from at least one target, the reflected radar signals are processed by resolving ambiguities associated with a range-Doppler detection based on unique pulse repetition frequencies (PRF)s associated with respective chirp groups of the reflected radar signals. Phase compensation is applied to compensate for motion-induced phased biases and, thereafter, Doppler estimates are reconstructed to provide a dealiased version of the reflected radar signals.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes attaching a first end of a first bond wire to a first conductive lead and a second end of the first bond wire to a first bond pad of a first semiconductor die. A conductive lead extender is affixed to the first conductive lead by way of a conductive adhesive, the lead extender overlapping the first end of the first bond wire. A first end of a second bond wire is attached to the lead extender, the first end of the second bond wire conductively connected to the first end of the first bond wire.

Abstract: Embodiments of a method and an apparatus for multi-link communications are disclosed. In an embodiment, a method for multi-link communications involves announcing, by a non-access point (non-AP) multi-link device (MLD) to an access point (AP) MLD, a frame exchange restriction in an enhanced multi-link operation, receiving, by the AP MLD from the non-AP MLD, the frame exchange restriction, and transmitting, by the AP MLD to the non-AP MLD, an initial frame according to the frame exchange restriction.

Abstract: A GPIO includes a transmitter having an output stage connected to the I/O pad and adapted to supply transmit data to an I/O pad in response to output data generated by a low voltage core logic operating within a functional voltage range for transmit operations; a receiver adapted to supply receive data to the low voltage core logic operating within the functional voltage range in response to input data received at the I/O pad for receive operations; a VLV transmitter adapted to supply VLV transmit data to the output stage of the transmitter and not directly to the I/O pad in response to output test data generated by the low voltage core logic; and a VLV receiver adapted to supply VLV receive data to the low voltage core logic operating within a low core supply voltage range in response to input data received from the output stage of the transmitter.

Abstract: A continuous-time delta-sigma modulator, CTDSM (400, 500, 700, 800) is described that comprises: an operational transconductance amplifier, OTA, (406, 506, 706, 806) having an input port (404, 504, 719, 739, 819, 839) configured to receive an analog input signal and an output port (408, 508, 707, 708, 807, 808); an input low pass filter network comprising at least one input resistor, R1, (402, 502, 702, 722, 802, 822) at least one first shunt capacitor, C1, (403, 503, 703, 803) and at least one feedback resistor, Rdac (410, 510, 710, 810, 730, 830) connected to the input port of the OTA; an output filter network comprising a shunt second resistor, R2, (415, 515, 715, 815) in parallel to a second shunt capacitor, C2, (414, 514, 714, 814), and coupled to the output port (408, 508, 707, 708, 807, 808) of the OTA; a quantizer (413, 513, 713, 813) connected to the output filter network and having at least one output connected to the input port of the OTA via the at least one feedback resistor, Rdac; and wherein th

Abstract: A wireless receiver wireless receiver unit (200) having a plurality of antennas comprises a spatial phase corrector circuit (234) connected to a first and second receiver (220, 222) and comprises: a computation circuit (330) configured to generate a spatial-covariance matrix, SCM, of a received first and second AM signal; a signal decomposition circuit (334) configured to generate an Eigen-value decomposition, EVD, (336) of the SCM; and a processor (340) configured to analyse the EVD of the SCM of the received first and second AM signal and select and output a principal Eigen-vector that is representative of at least a first weight (350) and a second weight (352). A combiner (240) is configured to apply the first weight (350) to the first AM signal received and apply the second weight (352) to the second AM signal received and coherently combine and output (250) the received weight-applied first and second AM signal.

Abstract: In one embodiment, a near field communication (NFC) device is provided, comprising: a communication unit configured to be communicatively coupled to an NFC reader; a processing unit configured to use a plurality of emulated cards for executing one or more applications; a profile determination unit configured to determine a polling profile of said NFC reader, wherein the polling profile represents a sequence of predefined radio frequency (RF) transmission events, and wherein the profile determination unit is configured to determine said polling profile by comparing a detected sequence of RF transmission events with one or more predetermined sequences; a card selection unit configured to select a specific one of said emulated cards for use by the processing unit in dependence on the polling profile determined by the profile determination unit. In another embodiment, a corresponding method of operating an NFC device is conceived.

Abstract: An electronic device substrate with a substantially planar surface formed from an electrically non-conductive material is provided with one or more metalized pads on the substantially planner surface. Each of the one or more metalized pads is surrounded by and coplanar with the first electrically nonconductive material along an outer boundary of the metalized pad. The metalized pad is patterned such that portions of the metalized pad form metalized fingers that extend radially from the outer boundary of the metalized pad in an interdigitated arrangement with the first electrically nonconductive material. The metalized pad has a solderable surface.

Abstract: There is described a method of determining an initial transmission phase offset in an NFC device configured to operate in NFC card mode only, wherein the NFC device comprises an NFC chip and a matching circuit. The method comprises: determining an initial RF matching resonance frequency of the NFC device utilizing an internal oscillator of the NFC chip; reading correction data from a non-volatile memory of the NFC chip, the correction data being indicative of a frequency offset of the internal oscillator relative to a nominal oscillator frequency; determining a corrected RF matching resonance frequency of the NFC device based on the initial RF matching resonance frequency and the correction data; and determining the initial transmission phase offset based on the corrected RF matching resonance frequency. Furthermore, a device and a method of manufacturing an NFC device are described.

Abstract: In a method for generating a physical layer (PHY) data unit for transmission via a communication channel, information bits to be included in the PHY data unit are received. A number of padding bits are added to the information bits. The number of padding bits is determined based on respective virtual values of each of one or more encoding parameters. The information bits are parsed to a number of encoders and are encoded, using the number of encoders, to generate coded bits. The coded bits are padded such that padded coded bits correspond to respective true values of each of the one or more encoding parameters. The PHY data unit is generated to include the padded coded bits.