Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.

Abstract: Embodiments of bidirectional repeaters and communications systems are disclosed. In an embodiment, a bidirectional repeater includes a digital state machine configured to control the bidirectional repeater to operate under a functional mode or under a bypass mode and a bypass mode driver configured to automatically detect a direction of signal through input/output (I/O) terminals of the bidirectional repeater and to allow a signal to pass through the bidirectional repeater based on the direction of signal under the bypass mode.

Abstract: Embodiments of sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a bias compensation circuit configured to measure a biasing condition of a first OTA of the pair of OTAs and to apply the biasing condition of the first OTA to a second OTA of the pair of OTAs to reduce Total Harmonic Distortion Plus Noise (THD+N) in the sigma-delta ADC circuit. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.

Abstract: A magnetoresistive random access memory (MRAM) array includes a data array and a sensor array. Each MRAM cell includes a Magnetic Tunnel Junction (MTJ). Each MRAM cell of the data array stores a data bit. A first and second column of the sensor array are connected to form a sensor column which includes sensor cells, each formed by a first MRAM cell in the first column together with a second MRAM cell in the second column along a same word line. Only one of a first MTJ of the first MRAM cell or second MTJ of the second MRAM cell is used as an MTJ of the sensor cell, and drain electrodes of select transistors of the first and second MRAM cells are electrically connected. Read circuitry provides read data from the data array and a sensor output indicative of a rupture state of an MTJ of the sensor array.

Abstract: In an IEEE 802.11 wireless system, a wireless STA is configured to access a secondary channel by receiving an inter-BSS PPDU which identifies a transmission channel bandwidth for the inter-BSS PPDU and TXOP duration, and then accessing a secondary channel which excludes the transmission channel bandwidth identified by the inter-BSS PPDU and a primary 20 MHz channel for the wireless STA device from a basic service set (BSS) operating bandwidth associated with the wireless STA device before exchanging one or more frames on the secondary channel during the TXOP duration without using the primary 20 MHz channel for the wireless STA device, and then switching back to the primary 20 MHz channel before the TXOP duration ends.

Abstract: A Doherty amplifier includes a peaking amplifier, a carrier amplifier, and a combining node electrically connected to the carrier amplifier and the peaking amplifier. The Doherty amplifier includes a harmonic control circuit coupled to the combining node. The harmonic control circuit includes an inductor and a capacitor and the inductor and capacitor are connected in series between the first current conducting terminal and a ground reference node. An inductance value of the inductor of the harmonic control circuit and a capacitance value of the capacitor of the harmonic control circuit are selected to terminate second order harmonic components of a fundamental frequency of a signal generated by the carrier amplifier.

Abstract: A sensor interface circuit includes a continuous-time capacitance-to-voltage (C/V) converter having C/V input and output ends, the C/V input end being configured for electrical connection with first and second sense nodes of a capacitive sensor. A filter circuit is electrically coupled to the C/V output ends. The filter circuit has first and second resistors at corresponding first and second filter input ends of the filter circuit, a capacitor connected between first and second filter output ends of the filter circuit, and a chopper circuit interposed between the first and second filter input ends and the first and second filter output ends. A buffer circuit is electrically coupled with the first and second filter output ends of the filter circuit. The filter circuit applies low pass filtering of sense signals from the capacitive sensor before sampling and demodulation operations to reduce high-frequency interference in the sense signals.

Abstract: Overmolded microelectronic packages containing knurled base flanges are provided, as are methods for producing the same. In various embodiments, the overmolded microelectronic package includes a molded package body, at least one microelectronic device contained in the molded package body, and a base flange to which the molded package body is bonded. The base flange includes, in turn, a flange frontside contacted by the molded package body, a device attachment region located on the flange frontside and to which the at least one microelectronic is mounted, and a knurled surface region. The knurled surface region includes a first plurality of trenches formed in the base flange and arranged in a first repeating geometric pattern. The molded package body extends or projects into the first plurality of trenches to decrease the likelihood of delamination of the molded package body from the base flange.

Abstract: A method is provided for protecting a machine learning (ML) model from a side channel attack (SCA). The method is executed by a processor in a data processing system. The method includes generating a first random bit. A first weighted sum is computed for a first connection between a node of a first layer and a node of a second layer of the ML model. The first weighted sum for the first connection is equal to a multiplication of the weight of the first connection multiplied by an input to the selected node. In the multiplication, one of the weight or the input is negated conditioned on a value of the random bit. A first output including the computed first weighted sum is provided to one or more nodes of a second layer of the plurality of layers.

Abstract: Embodiments of redrivers and resistive termination units for redrivers are disclosed. In an embodiment, a resistive termination unit for a redriver includes a resistor connected to an input/output terminal of the redriver, a first switch connected to the resistor and to a supply voltage of the redriver, a second switch connected to the first switch and configured to be turned on or off in response to a change in the supply voltage of the redriver, and a control circuit connected to the first switch through the second switch and configured to generate a control signal for the first switch.

Abstract: An attenuation device for a CAN transceiver comprises two device output nodes configured to electrically couple the attenuation device via the device output nodes between two transceiver terminals of the CAN transceiver. The attenuation device is configured to change from a first device state to a second device state when a common mode voltage is applied to the device output nodes that is either greater than a first reference voltage or less than a second reference voltage that is less than the first reference voltage. The attenuation device causes a first electrical output resistance at each device output node during the first device state and causes a second electrical output resistance at each device output node during the second device state in which the second output resistance is less than the first output resistance.

Abstract: A multi-cell battery apparatus is provided, according to certain aspects, including a battery with a plurality of voltage-stacked battery cell circuits, a switchable resistive-divider circuit and a control circuit. The control circuit selectively activates the switchable resistive-divider circuits and, in response to the respective switchable resistive-divider circuits being selectively activated, the control circuit measures the controlled-load voltage drops. These aspects are used to allow open load detection without interfering with the cell balancing mechanism and the accuracy of the redundant measurements performed on these pins in a battery management system.

Abstract: A scalable neural network accelerator may include a first circuit for selecting a sub array of an array of registers, wherein the sub array comprises LH rows of registers and LW columns of registers, and wherein LH and RH are integers. The accelerator may also include a register for storing a value that determines LH. In addition, the accelerator may include a first load circuit for loading data received from the memory bus into registers of the sub array.

Abstract: A multiphase digital frequency synthesizer including a multiphase ring oscillator that provides phased clock signals, a clock divider that divides a phased clock signal by an integer value and a carry value to provide a divided clock signal, positive select circuitry that determines and updates a positive select value with accumulation and a modulo function based on a fractional division factor updated with successive cycles of the divided clock signal, carry circuitry that determines the carry value based on a number of the phased clock signals, positive multiplex circuitry that selects from among the phased clock signal using the positive select value for providing a positive multiplexed clock signal, and fractional phase addition circuitry that provides a first output clock signal based on a selected phased clock signal, the divided clock signal, and the positive multiplexed clock signal. Similar negative select circuitry and duty cycle correction circuitry may be included.

Abstract: Stabiliser circuits and methods are disclosed, for stabilizing a voltage at a gate driver terminal of a gate-driver for a driven transistor to a one of a high voltage and a low voltage, the stabilizer circuit comprising: a first transistor and a second transistor having respective first and second main terminals and connected in series between the gate voltage terminal and a first reference voltage terminal; and a low-pass filter connected between a control terminal of the first transistor and the gate driver terminal; wherein the first transistor is configured to have a threshold voltage which is less that a threshold voltage of the driven transistor; and the second transistor has a control terminal which is configured to be connected to a voltage which is an oppositive of the voltage at the gate driver terminal.

Abstract: The disclosure relates to a transceiver device for communicating between a network protocol controller and a network bus, the transceiver device comprising: transceiver circuitry configured to transmit and receive data on the network bus using a first physical layer protocol; and monitoring circuitry configured to determine a measured property of the network bus, in which the transceiver device is configured to: determine whether the measured property indicates an error condition; and reconfigure the transceiver circuitry to transmit and receive data on the network bus using a second physical layer protocol in response to determining the error condition.

Abstract: Packaged semiconductor devices are disclosed, comprising: a semiconductor die having a top major surface with a plurality of contact pads thereon, and four sides, wherein the sides are stepped such that a lower portion of each side extends laterally beyond a respective upper portion; encapsulating material encapsulating the top major surface and the upper portion of each of the sides wherein the semiconductor die is exposed at the lower portion of each of the sides; a contact-redistribution structure on the encapsulating material over the top major surface of the semiconductor die; a plurality of metallic studs extending through the encapsulating material, and providing electrical contact between the contact pads and the contact-redistribution structure. Corresponding methods are also disclosed.

Abstract: A wireless communication system, apparatus, and methodology are described for enabling wireless communication devices to generate extended range Physical Layer Protocol Data Units (PPDUs) for wireless transmission to a destination communication devices by generating, at a first wireless communication device, a data sequence in which a plurality of repeated data symbols are encoded for wireless transmission to the second communication device, and then applying a scrambling sequence that is known to the first and second communication devices to the data sequence to generate an output data sequence wherein the plurality of repeated data symbols are pseudo-randomized prior to performing an inverse Fourier transform on the output data sequence.

Abstract: A detector circuit is described for start signaling in an eUSB repeater. In an example, a circuit includes an analog differential transceiver configured to receive a differential data signal from a differential data bus and configured to drive a differential data signal to the differential data bus, an analog single-ended transceiver configured to receive a single-ended data signal from a single-ended data bus and configured to drive a single-ended data signal to the single-ended data bus, repeater logic coupled to the analog differential transceiver and the analog single-ended transceiver to repeat data signals between the differential data bus and the single-ended data bus, the repeater logic having an active state and a low power state, and a detection circuit coupled to the analog single-ended transceiver to detect a start signal on the single-ended data bus and to generate a wake signal to the repeater logic upon detecting the start signal.

Abstract: An integrated circuit package comprising an encapsulant, a semiconductor die in the encapsulant the semiconductor die comprising a plurality of die terminals, an integrated waveguide launcher, wherein the integrated waveguide launcher is connected to one of the die terminals and a land grid array provided on a bottom surface of the package. The land grid array comprises a plurality of package terminals, each package terminal configured to be soldered to a printed circuit board, and an opening, wherein the opening is aligned with the integrated waveguide launcher.