Abstract: An aspect of the invention is directed towards a data processing system and method including a transaction scheduler configured to process transactions, a tag control circuit coupled to the transaction scheduler configured to detect a fault by comparing output signals, and a controller coupled to the tag control circuit. The controller is configured to receive a transaction request identifying a transaction, generate a unique tag value for the transaction request, load the unique tag value into the transaction scheduler, determine a current unique tag value associated with the transaction being executed, and generate a fault. The system is further configured to generate fault when: (i) the current unique tag value is not found, or (ii) the transactions timeout after a predetermined number of cycles.

Abstract: A context switching system includes a processor and a scheduler. The processor is configured to execute a first thread. A first context associated with the first thread is stored in a register set of the processor. While the first thread is being executed, the scheduler is configured to select a second thread from a set of threads, and receive and store a second context associated with the second thread in a register set of the scheduler. The second thread is to be scheduled for execution after the first thread. The scheduler is further configured to swap the first and second contexts when the execution of the first thread is halted, thereby executing the context switching. Further, the processor is configured to execute the second thread based on the second context. While the second thread is being executed, the first context is stored in the data memory.

Abstract: A peak current detector is integrated into a power supply, such as a power management integrated circuit, to detect glitch attacks imposed on the power rails inside the power supply. Integrated circuitry being supplied by the power supply periodically checks the state of the power supply via a secure communication channel to obtain the detected peak current values, which allow the integrated circuitry to detect those attacks and react accordingly to any possible threats.

Abstract: Embodiments of equalizers are disclosed. In an embodiment, an equalizer includes a first signal path segment that includes a first plurality of serially connected transistors and current sources, a second signal path segment that includes a second plurality of serially connected transistors and current sources, and at least one termination resistor connected to the first and second signal path segments. The first plurality of serially connected transistors and current sources includes a first current source and a second current source connectable to a reference voltage and a first transistor and a second transistor connected between input terminals of the equalizer and the first and second current sources, where the first signal path segment further includes at least one resistor connected between the first and second current sources.

Abstract: In an 802.11be wireless system, a receiving station device signals a packet padding capability in a wireless area network in accordance with an Extremely High Throughput (EHT) communication protocol by constructing a MAC control management frame to include an EHT capability element indicating whether a packet extension value longer than 16 ?s is supported by the receiving station device, where one or more fields in the EHT capability element include (1) a common nominal packet padding field having a plurality of values to signal different packet extension values for use with all transmission constellations, spatial streams NSS, and resource unit (RU) allocations supported by the first STA device, including at least one packet extension value longer than 16 ?s; and/or (2) a PHY packet extension threshold (PPET) field comprising a plurality of PPET values to signal packet extension values including at least one packet extension value longer than 16 ?s.

Abstract: A leadless semiconductor package includes a conductive base having a plurality of apertures formed around a perimeter of the conductive base and extending from a first surface to an opposing second surface of the conductive base. The semiconductor package further includes an IC die having a third surface facing the first surface of the conductive base and having a plurality of conductive pillars disposed thereon. Each conductive pillar extends from the third surface to the first surface via a corresponding aperture. A dielectric fill material is disposed in the apertures and insulates the conductive pillars from the conductive material of the conductive base. An opening of an aperture at the second surface, the bottom end of the conductive pillar disposed therein, and the dielectric fill material at the opening of the aperture at the second surface together form a surface mount pad for mounting the semiconductor package to a corresponding pad of a circuit board.

Abstract: Aspects of the present disclosure are directed to radar communications with disparate pulse repetition intervals, as may be implemented with radar transmission, receiver and processing circuitry. As may be utilized in accordance with one or more embodiments herein, time division multiplexing (TDM) multi-input multi-output (MIMO) radar signals are transmitted by transmitting sets of successive radar signals, each set having a pulse repetition interval (PRI) that is different than the PRI of sets of radar signals transmitted in another one of the sets. Positional characteristics of a target may be ascertained based on the PRI used in each of the sets and on phase characteristics of ones of the radar signals reflected from the target.

Abstract: A method, device and a radar system for determining phase error caused by impairments in a phase rotator comprises (a) forcing the Q path of the phase rotator to zero and obtaining a first sequence of successive measurement values, (b) forcing the I path of the phase rotator to zero and obtaining a second sequence of successive measurement, (c) forming a sequence of successive measurement value pairs, each measurement value pair comprising one measurement value from the first sequence of successive measurement values and one measurement value from the second sequence of successive measurement values (d) calculating an actual phase value for each of the successive measurement value pairs, and (e) determining the phase error by comparing the actual phase values with the corresponding reference phase values.

Abstract: A device comprises a substrate and a stacked bond ball structure. The substrate comprises a bond pad, and the stacked bond ball structure comprises a first and a second bond ball. The first bond ball is in contact with the bond pad, and the second bond ball is positioned on the first bond ball. The stacked bond ball structure is configured to be coupled to a resistance-sensing circuit, such that a resistance of an interface between the first bond ball and the bond pad can be measured to determine an amount of degradation of the interface between the first bond ball and the bond pad. In some implementations, the device further comprises a controller configured to obtain a measured resistance of the interface from the resistance-sensing circuit and determine the amount of degradation of the interface based at least in part on the measured resistance.

Abstract: The disclosure relates to monitoring of feedback systems such as phase lock loops. A system is disclosed, comprising: a feedback circuit (100); and a monitoring module (190). The monitoring module (190) is configured to: i) receive actual values of at least one state variable describing the state of the feedback circuit at a first time; ii) determine a predicted future value of the at least one state variable at a second time from the actual values at the first time using a model of the feedback circuit; iii) receive actual values of the at least one state variable at the second time; iv) compare the predicted future value of the at least one state variable at the second time with the actual value of the at least one state variable at the second time; and v) determine whether the feedback circuit has a fault condition, depending on the results of step iv).

Abstract: A signal coupler (100) comprising: a main-transmission-line (114) that extends in a longitudinal direction within a substrate (102) between an input port and an output port; and a coupled-transmission-line (116) that extends in the longitudinal direction within the substrate (102) between a coupled port and a termination port. The coupled-transmission-line (116) is in a second layer (110). The main-transmission-line (114) comprises a first-portion (120) in a first layer (108), a second-portion (122) in a second layer (110), and a third-portion (124) in a third layer (112). At least part of the first-portion (120) is spaced apart from the coupled-transmission-line (116) in a depth direction. At least part of the second-portion (122) is spaced apart from the coupled-transmission-line (116) in the depth direction. At least part of the third-portion (124) is spaced apart from the coupled-transmission-line (116) in the depth direction.

Abstract: One example discloses a power application circuit, including: a first power application circuit, configured to receive an enable signal and a first voltage; wherein the first power application circuit is configured to output the first voltage at a first current after a first delay from when the enable signal is received; and a second power application circuit, configured to receive the enable signal and a second voltage; wherein the second power application circuit is configured to output the second voltage at a second current after a second delay from when the enable signal is received.

Abstract: A boost converter comprises a comparator circuit including: a first input port configured to receive an off-time sawtooth voltage a second input port configured to receive an on-time sawtooth voltage, the comparator circuit comparing the off-time sawtooth voltage and on-time sawtooth voltage to generate trigger signal including a differential ripple voltage that is output by an output port to a power stage circuit. The boost converter further comprises a reference voltage source that provides a reference voltage to the first input port and a feedback circuit that provides the on-time sawtooth voltage to the second port, wherein the differential ripple voltage emulates an inductor current or voltage of an output capacitor of the power stage circuit.

Abstract: A transistor device includes a substrate, a first current-carrying region having a first lateral width, and a second current-carrying region. A first trench is formed between the first current-carrying region and the second current-carrying region. The first trench includes a first vertical component sidewall coupled to the first current-carrying region and a second vertical component sidewall coupled to the second current-carrying region. A first termination region includes a first termination portion coupled to the first current-carrying region, a second termination portion coupled to the second current-carrying region, and a first trench termination portion coupled to the first trench. The first trench and the first trench termination portion surround a portion of the first current-carrying region, and the second current-carrying region and the second termination portion surrounds a portion of the first trench and the first trench termination portion.

Abstract: Provided is a current-sensing circuit that includes a power-supply line providing electrical power to a high side of a load, a high-side field-effect transistor (FET) component between the power-supply line and the high side of the load, and a low-side FET component coupled to a low side of the load. Gate signals continually repeat a cycle that includes: a first part in which the high-side FET component is turned on and the low-side FET component is turned off, and a second part in which the high-side FET component is turned off and the low-side FET component is turned on. In addition, a single transconductance stage is configured to: input signals indicating a voltage drop across whichever one of the high-side FET component or the low-side FET component currently is on, and output a signal indicating a current flow that corresponds to such voltage drop.

Abstract: Embodiments of a device and a method for multi-link communications are disclosed. In an embodiment, a device includes a processor configured to identify that an update event has occurred on a first link of an access point (AP) multi-link device (MLD), and transmit a management frame on a second link, where the management frame includes a Change Sequence field and a multi-link (ML) element that indicates the update event.

Abstract: A system for verifying memory-read capabilities includes a memory device, having a memory cell array that is encoded with verification information, and a memory-read controller, coupled to the memory device and configured to execute stored process steps. The verification information includes first bit values encoded in a first row of the memory cell array and second bit values encoded in a second row of the memory cell array. Each of the second bit values on a same bit line as a corresponding one of the first bit values has an inverse value as the corresponding one of the first bit values. The stored process steps include steps to: read the verification information from the memory device; determine, by comparison to a pre-stored bit string, whether the first bit values and the second bit values are correct; and in response to an affirmative determination, initiate normal data-read operations.

Abstract: Memory built-in self-test (MBIST) circuitry for a disruptive memory includes an address sequencer configured to select an address with the disruptive memory as a test location, and control circuitry configured to direct a test sequence including a plurality of test operations on the test location. The control circuitry includes a first fault counter and a second fault counter, in which the control circuitry is configured to, after each test operation of the test sequence, determine whether to selectively update a first fault counter and whether to selectively update a second fault counter. The address sequencer, after completion of the test sequence, selects a next address within the disruptive memory as a next test location.

Abstract: A Quad Flat No-Lead (QFN) package comprises a semiconductor die, a lead frame and molding compound. The lead frame comprises a die pad having a substantially rectangular inner part and a plurality of protrusions around the periphery thereof and contiguous therewith and extending outwardly therefrom, and a plurality of leads around the four sides of the die-pad. The molding compound encapsulates the semiconductor die and forming the package. The molding compound has a respective moat therein between each side of the die pad and a respective set of leads. The die pad has a plurality of trenches extending from the second surface of the die pad towards the first surface at least in the inner part of the die pad. The plurality of the trenches each extend across a protrusion to the moat.

Abstract: A method of dynamic configuration of reaction policies in virtualized fault management system includes disabling a fault handler circuit comprising a reaction core in response to receiving a request to modify a respective first reaction policy including a plurality of first recovery actions of the reaction core, wherein each of the first recovery actions is responsive to a respective fault indication. At least one event status is cleared from an event table of the fault handler circuit. The at least one event status is set in response to the fault handler circuit receiving the respective fault indication. The reaction core is configured with a second reaction policy including a plurality of second recovery actions.