Patents Assigned to NXP
  • Patent number: 12119300
    Abstract: A device having a reference transistor fabricated within the same semiconductor substrate as a primary transistor (e.g., configured for use in a radiofrequency amplifier or other active circuit) has a shared metallization area coupled to a current terminal of both transistors configured to shield a control terminal of the reference transistor from coupling of alternating current interference from alternating currents within the primary transistor.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: October 15, 2024
    Assignee: NXP USA, Inc.
    Inventors: Humayun Kabir, Ibrahim Khalil, Daniel Joseph Lamey, Yu-Ting David Wu
  • Patent number: 12120760
    Abstract: One example discloses a multi-link device (MLD) within a wireless local area network (WLAN), including: a controller configured to generate a management frame having a set of multi-link information elements (ML IEs); wherein the MLD is configured to be coupled to a set of PHY-layer links; and wherein the controller is configured to perform a multi-link setup with a second MLD using the set of ML IEs over the PHY-layer links.
    Type: Grant
    Filed: October 23, 2021
    Date of Patent: October 15, 2024
    Assignee: NXP USA, Inc.
    Inventors: Liwen Chu, Young Hoon Kwon, Hongyuan Zhang
  • Patent number: 12113571
    Abstract: In accordance with a first aspect of the present disclosure, a communication device is provided, comprising: a receiver circuit configured to receive a signal; a controller configured to control said receiver circuit, wherein said controller is configured to cause said receiver circuit to operate either in a complex receiver mode or in a real receiver mode; wherein the controller is configured to cause said receiver circuit to operate in the real receiver mode until the signal is successfully acquired. In accordance with a second aspect of the present disclosure, a corresponding method of operating a communication device is conceived.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: October 8, 2024
    Assignee: NXP B.V.
    Inventors: Jan Dutz, Gert Holler, Wolfgang Küchler
  • Patent number: 12113520
    Abstract: A bootstrap switch circuit includes a transistor-based switch controlled by a first gate signal and a leakage protection transistor controlled by a second gate signal configured to reduce gate induced drain leakage in the transistor-based switch A first gate driver is included that produces a first gate signal at its output so that the first gate signal turns on the transistor-based switch during a sampling mode and turns off the transistor-based switch during a hold mode. A second gate driver is included that produces a second gate signal at its output and to receive the output signal of the bootstrap switch circuit so that the second gate signal turns on the leakage protection transistor during the sampling mode and turns off the leakage protection transistor during the hold mode and the second gate signal is based upon the output signal of the bootstrap switch circuit.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: October 8, 2024
    Assignee: NXP B.V.
    Inventors: Saurabh Goyal, Krishna Thakur
  • Patent number: 12114472
    Abstract: A Radio Frequency, “RF”, component and a method of making the same. The component includes a first electrically conductive signal member for conveying an RF signal and a second electrically conductive signal member for conveying an RF signal. The component also includes a barrier located between the first signal member and the second signal member electromagnetically to shield the first and second signal members from each other. The barrier includes a first row of electrically conductive shielding members spaced apart along a longitudinal axis of the first row, and a second row of electrically conductive shielding members spaced apart along a longitudinal axis of the second row. Each shielding member includes a polyhedron. The shielding members of the first row are offset with respect to the shielding members of the second row to prevent a direct line of sight between the first signal member and the second signal member.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: October 8, 2024
    Assignee: NXP B.V.
    Inventors: Philipp Franz Freidl, Mustafa Acar, Antonius Hendrikus Jozef Kamphuis, Jan Willem Bergman
  • Patent number: 12113909
    Abstract: A method and electronic device are provided for decrypting homomorphically encrypted (HE) data. The method may include generating, in the electronic device, result metadata that specifies a size of the HE data to be decrypted. The electronic device generates or collects HE input data and the result metadata. The HE input data and the encrypted result metadata are transmitted to a cloud server in a cloud environment to allow the cloud server to perform computations using the HE input data. The cloud server is enabled by the hardware device to send a result of the computations on the HE input data to a secure element (SE) for decryption. A relatively secure online connection is established to the SE in the cloud environment. The SE is enabled by the electronic device to decrypt the result of the computations on the HE input data as specified by the result metadata.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: October 8, 2024
    Assignee: NXP B.V.
    Inventors: Adrian Marotzke, Leonard Clemens Püttjer
  • Patent number: 12113550
    Abstract: A method for encoding data to be stored in a memory, including: encoding the data to be stored in memory with an error correcting code (ECC) as first encoded data, wherein the ECC is configured to have a minimum Hamming distance of at least 4t+1 in order to correct up to t bit errors and detect up to 3t bit errors where t?1; determining a Hamming weight of the first encoded data; encoding the determined Hamming weight, wherein for all higher Hamming weights the encoding should have at least 2t+1 bit-positions that change from 1 to 0 per Hamming weight; concatenating the first encoded data and the encoded Hamming weight as concatenated data; and storing the concatenated data in the memory.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: October 8, 2024
    Assignee: NXP B.V.
    Inventor: Björn Fay
  • Patent number: 12114383
    Abstract: Embodiments of an apparatus and method are disclosed. In an embodiment, a method of multi-link communications involves at an access point (AP) multi-link device, allocating Association IDs (AIDs) to non-AP multi-link devices, including allocating one of the AIDs to each of the non-AP multi-link devices, and at the AP multi-link device, generating a first indication element for the AIDs to indicate a buffered data configuration at the AP multi-link device for the non-AP multi-link devices.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: October 8, 2024
    Assignee: NXP USA, Inc.
    Inventors: Young Hoon Kwon, Liwen Chu, Hongyuan Zhang, Hui-Ling Lou
  • Patent number: 12109897
    Abstract: In an embodiment, there is provided a battery management method for a vehicle comprising a plurality of batteries. According to another embodiment there is a control unit for performing the battery management method. The battery management method comprising detecting an incoming hazard; predicting an impact of the incoming hazard from one or more sensors coupled to the vehicle; determining a course of action to be taken in response to the predicted impact; and controlling one or more batteries of the plurality of batteries according to the determined course of action.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: October 8, 2024
    Assignee: NXP B.V.
    Inventors: Alphons Litjes, Hendrik Johannes Bergveld, Alexander Vogt, Cristian Pavao Moreira
  • Patent number: 12114259
    Abstract: Various embodiments relate to a method performed by a multi-link device (MLD) access point to establish a target wake time (TWT) with a MLD station, wherein a plurality of links are established between the MLD access point and the MLD station, including: transmitting, by the MLD access point, a TWT set up frame to the MLD station configured to indicate whether the TWT set up frame is applied to multiple links of the plurality of links; and negotiating, by the MLD access point, a TWT agreement with the MLD station via one of the multiple links with the MLD station, wherein the TWT agreement applies to all of the indicated multiple links.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: October 8, 2024
    Assignee: NXP USA, Inc.
    Inventors: Liwen Chu, Hongyuan Zhang, Young Hoon Kwon, Huiling Lou
  • Patent number: 12113647
    Abstract: An apparatus comprising a first and second terminal configured to couple the apparatus to a first and second bus wire of a communication bus; a transceiver arrangement for communicating with one or more network nodes via the communication bus, the transceiver arrangement configured to provide and receive differential signalling according to a communication scheme to/from the communication bus, wherein the communication scheme defines at least a voltage to be used to provide said differential signalling; the apparatus configured to: based on a fault detection signal indicative of the occurrence of a fault in at least the communication bus, transmit a reconfiguration signal for the network nodes and wherein at least part of the reconfiguration signal has a high-voltage-level comprising a voltage higher than that defined in the communication scheme for said differential signalling; and wherein said reconfiguration signal is configured to cause the network nodes to switch single-ended signalling.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: October 8, 2024
    Assignee: NXP B.V.
    Inventors: Lucas Pieter Lodewijk van Dijk, Martin Wagner, Gerald Kwakernaat
  • Patent number: 12105114
    Abstract: A microelectromechanical systems (MEMS) accelerometer comprises a compliant spring structure with a first beam, a second beam, and a rigid structure. One end of the first beam and one end of the second beam are coupled to the rigid structure and a proof mass is coupled to another end of the second beam. Further, a spring anchor is coupled to another end of the first beam. In response to the proof mass moving, an extension coupled to the rigid structure moves in an opposite direction to motion of the proof mass to contact the proof mass and stop the movement of the proof mass.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: October 1, 2024
    Assignee: NXP USA, Inc.
    Inventors: Aaron A. Geisberger, Jun Tang
  • Patent number: 12107143
    Abstract: A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region that is connected to a collector region via semiconductor material formed in an opening in one or more dielectric layers interposed between the extrinsic base region and the collector region. The extrinsic base region may be formed from monocrystalline semiconductor material, such as silicon or silicon germanium, via selective epitaxial growth. An intrinsic base region may be formed adjacent to the extrinsic base region and may be interposed directly between the collector region and an intrinsic emitter region. A HBT with such an arrangement may have reduced base-collector capacitance and reduced base resistance compared to some conventional HBTs.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: October 1, 2024
    Assignee: NXP B.V.
    Inventors: Ljubo Radic, Johannes Josephus Theodorus Marinus Donkers, Bernhard Grote
  • Patent number: 12107525
    Abstract: A power module may include multiple transistors each respectively having a first current-carrying terminal coupled to a voltage supply, a second current-carrying terminal coupled to an output node, and a control terminal, multiple output driver stages each coupled to the control terminal of a respectively different transistor of the transistors, and a driver module. The driver module may include multiple pre-drivers each coupled to a respectively different output driver stage of the output driver stages and a control module having an input and having multiple outputs coupled to the pre-drivers. The control module may be configured to receive a control signal at the input and to selectively control the pre-drivers to drive at least a subset of the plurality of transistors via the output driver stages based on the control signal.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: October 1, 2024
    Assignee: NXP USA, Inc.
    Inventors: Jerry Rudiak, Ibrahim Shihadeh Kandah, Fred T. Brauchler
  • Patent number: 12105583
    Abstract: A fault recovery system includes various fault management circuits that form a hierarchical structure. One fault management circuit detects a fault in a functional circuit and executes a recovery operation to recover the functional circuit from the fault. When the fault management circuit fails to recover the functional circuit from the fault within a predetermined time duration, a fault management circuit that is in a higher hierarchical level executes another recovery operation to recover the functional circuit from the fault. Such a fault management circuit is required to execute the corresponding recovery operation within another predetermined time duration to successfully recover the functional circuit from the fault. The fault recovery system thus implements the hierarchical structure of fault management circuits to recover the functional circuit from the fault.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: October 1, 2024
    Assignee: NXP B.V.
    Inventors: Neha Srivastava, Hemant Nautiyal, Andres Barrilado Gonzalez
  • Patent number: 12106884
    Abstract: A radio frequency, RF, auto-transformer circuit (300, 700, 901) and method (1000) of constructing a RF auto-transformer are described. The RF, auto-transformer circuit (300, 700, 901) includes: an inner coil formed (1102) with a first metal layer (MT1) to create a first shunt inductor (302), wherein at least a portion of the inner coil is overlayed (1106) with a second metal layer (MT2) that creates a first series inductor (303) that exhibits inductive coupling to the first shunt inductor (302). An outer coil is formed (1104) with the first metal layer (MT1) that creates a second series inductor (304), where the outer coil is located adjacent the inner coil and provides inductive coupling between the second series inductor (304) and each of the first shunt inductor (302) and first series inductor (303).
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: October 1, 2024
    Assignee: NXP B.V.
    Inventors: Xin Yang, Mark Pieter van der Heijden
  • Patent number: 12099394
    Abstract: Systems and methods for preserving a decoupling capacitor's charge during low power operation of a logic circuit. An electronic circuit may include: a main voltage regulator coupled to a supply voltage terminal and configured to apply a first regulated voltage across a capacitor coupled in parallel with a logic circuit; a low power regulator coupled to the supply voltage terminal and configured to apply a second regulated voltage across the logic circuit; and a control circuit coupled to the low power regulator. The control circuit may be configured to: during a first mode of operation, allow the main voltage regulator to apply the first regulated voltage to the logic circuit, and, during a second mode of operation, allow the low power regulator to apply the second regulated voltage to the logic circuit and decouple the capacitor from the logic circuit while the low power regulator applies the second regulator voltage.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: September 24, 2024
    Assignee: NXP B.V.
    Inventors: Andre Gunther, Jeffrey Alan Goswick, Rob Cosaro
  • Patent number: 12101412
    Abstract: A plurality of objects that comprise an input to a cryptographic signing function. For each object in the plurality of objects, an output value yi of a hash function is calculated, where the value i is equal to an index value of the object, a compressed output value xi of a compression function is calculated, the output value yi from the computer readable memory, and the compressed output value xi is stored. For each object in the plurality of objects, an output value y?i of the hash function is calculated, where the value i is equal to the index value of the object, a compressed output value x?i of the compression function executed on the output value y?i is calculated, the output value x?i is determined to be equal to the output value xi, and the output value y?i is transmitted in an output data stream.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: September 24, 2024
    Assignee: NXP USA, Inc.
    Inventors: Tobias Schneider, Melissa Azouaoui, Christine van Vredendaal
  • Publication number: 20240313679
    Abstract: A method for Field Oriented Control (FOC) of a Permanent Magnet Synchronous Motor (PMSM) with a constant Power Factor Control (PFC) Loop includes measuring a rotor position of the PMSM. A plurality of stator voltages of the PMSM is controlled with a required direct (d)-axis current, a required quadrature (q)-axis current, the rotor position and a plurality of measured stator currents of the PMSM in a three-phase stationary reference frame. The required d-axis current is determined with a required power factor, the plurality of measured stator currents transformed into two-phase stationary reference frame, the measured stator currents transformed into a rotational reference frame, and each of a required ?-axis voltage and a required ?-axis voltage transformed into the two-phase stationary reference frame, wherein a power factor of the PMSM is controlled to be equal to the required power factor.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 19, 2024
    Applicant: NXP USA, Inc.
    Inventors: Michal Vidlak, Lukas Gorel, Tomas Kulig
  • Patent number: 12092496
    Abstract: As disclosed herein, circuitry and a method for providing a digitized voltage value of one capacitive sensor in which a second capacitive sensor is utilized for charge equalization. After charge equalization, an analog to digital converter (ADC) provides a digital value representative of the voltage of the one sensor.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: September 17, 2024
    Assignee: NXP USA, INC.
    Inventor: Vaclav Bajgar