Abstract: A method and apparatus are described for fabricating a high aspect ratio MEMS sensor device having an inertial transducer element formed in a multi-layer semiconductor structure, where the first inertial transducer element comprises a first monocrystalline semiconductor proof mass element and a second conductive electrode element separated from one another by an air sensing gap, and where at least a first sensing gap surface of the first monocrystalline semiconductor proof mass element is a first rough surface that has been selectively etched to reduce stiction between the first monocrystalline semiconductor proof mass element and the second conductive electrode element.

Abstract: Speed of plasma etching is regulated in regions prone to over-etching by providing an etch resistant structure, such as a metal saw bow, in the region. By adjusting dimensions, such as the length and width of the saw bow legs and an area defined by the saw bow legs, as well as a shape of the etch region through techniques such as chamfering, plasma etch speed in the region can be controlled with an intent to match the speed of etching in non-over-etched regions.

Abstract: There is described an RFID tag IC, comprising: i) an NFC interface configured to initiate a power-up, when coupled with an HF field, and receive a read command from an RFID device; ii) a non-volatile memory, wherein the non-volatile memory is configured to store a counter value; and iii) a processing unit configured to increment the counter value when coupled with the HF field, set an increment flag, when the increment is successful, and thereby block a further increment of the counter value, in particular when fulfilling the read command, and reset the increment flag after fulfilling the read command. Further, a communication system and a method of operating are described.

Abstract: An apparatus and method for measuring energy cell impedance. Time sequences representing each of a repetitive signal, an orthogonal-phase-repetitive signal at the characterizing frequency, and at least one term of a power series polynomial are generated. One of a current or voltage corresponding to the repetitive signal is applied to an energy cell. Contemporaneously with the applying, measured values of a current or voltage are measured. A set of correlation values between the measured values and the generated time sequences are determined. The set of correlation values are transformed into a set of fitted coefficients of a repetitive signal component and an orthogonal-phase-repetitive signal component at a characterizing frequency. An impedance of the energy cell at the characterizing frequency is determined based on a ratio of the fitted coefficients for the orthogonal-phase-repetitive component to the repetitive signal component.

Abstract: A battery pack comprises an enclosure; a plurality of network nodes that communicate with each other inside the enclosure and that generate a unique radio frequency (RF) signature; and a special-purpose computer processor that compares an incoming channel impulse response (CIR) of the unique radio frequency (RF) signature corresponding to an incoming packet to a plurality of stored valid RF CIR signatures and executes a resemblance metric to accept or reject the incoming packet.

Abstract: Disclosed is a UWB communication node comprising: a UWB communication unit configured to transmit one or more messages, to a plurality of external responder nodes and comprising a ranging control message defining a contention period, and further configured to receive one or more responses from said responder nodes during said contention period, each response including a response payload; a processor unit configured to use a common cryptographic session key to encrypt said messages; wherein the processing unit is further configured to use responder-specific session keys to decrypt the response payloads; wherein each individual one of said responder-specific cryptographic session keys is a unique key shared between the node and one of the external responder nodes. Corresponding systems methods and an associated computer program are also disclosed.

Abstract: A transistor with an emitter, base, and collector. The base includes a monocrystalline base layer. A sacrificial material is formed on the monocrystalline base layer. The sacrificial material is removed to expose a portion of the monocrystalline base layer. A base silicide includes a portion formed on the portion of the base monocrystalline base layer that was exposed by the removal of the sacrificial material.

Abstract: A switching device may include an input terminal, an output terminal, a primary switching transistor electrically coupled between the input terminal and the output terminal, and a cascode arrangement electrically coupled between the primary switching transistor and the input terminal. The cascode arrangement may include multiple cascode transistors, each having gate terminals coupled to nodes of a voltage divider that is coupled between a positive voltage supply and a reference voltage supply. Emitter-follower bipolar junction transistors (BJTs) may be configured to control voltages at the gate terminals of the primary switching transistor and the cascode transistors to accommodate changes in the output voltage at the output terminal.

Abstract: A circuit is disclosed, comprising: an inverter comprising first and second inverter transistors, each having: a gate terminal connected in common to a drive node, a source terminal, connected to respective first and second voltage rails, and a drain terminal connected to a common first resistor, wherein an inverter output node is connected between the first resistor and the drain terminal of a shorting one of the transistors; a tying transistor connected between the drive node and the voltage rails to which the shorting transistor is connected; a biasing circuit connected to the tying transistor's control terminal and configured to be controlled by a local drive signal and bias the tying transistor control terminal to a voltage such that the tying transistor ties the drive node of the relevant voltage rail in response to the drive signal having a first state; and a circuit for providing the local drive signal.

Abstract: Embodiments of RF amplifiers and packaged RF amplifier devices each include an amplification path with a transistor die, and an output-side impedance matching circuit having a T-match circuit topology. The output-side impedance matching circuit includes a first inductive element connected between the transistor output terminal and a quasi RF cold point node, a second inductive element connected between the quasi RF cold point node and an output of the amplification path, and a first capacitance connected between the quasi RF cold point node and a ground reference node. The RF amplifiers and devices also include a baseband termination circuit connected to the quasi RF cold point node, which includes a third inductive element, a resistor, and a second capacitance in series between the quasi RF cold point node and the ground reference node and a third capacitance between a baseband termination circuit node and the ground reference node.

Abstract: There is provided, a method for clock recovery in a RFID tag, the method includes receiving a RF field from a RFID reader. A field clock is generated from the received RF field, from which a clock recovery signal is generated. The RF field is modulated to produce a RF modulation. Generation of the clock recovery signal is paused while the RF field is being modulated. A modulation envelope signal is generated and used for load modulation. Generation of the clock recovery signal at the end of the RF modulation is resumed after a delay of one clock cycle from a falling edge of the modulation envelope signal. In another embodiment of the method, instead of adding the delay, a differential amplifier is used to increase RF field detection sensitivity. The method and the RFID tag ensures synchronized resumption of a PLL clock and the clock recovery signal.

Abstract: A method, a system, and a device for wireless localization are disclosed. In an embodiment, the method includes performing, by a localization device, Two-Way Ranging (TWR) and Time Difference of Arrival (TDOA) in parallel, where the TWR is performed with a receiving device to determine a distance between the localization device and the receiving device, and the TDOA is performed with anchors to determine a geolocation of the localization device, and determining, using the distance and the geolocation, a position of the localization device relative to the receiving device.

Abstract: A Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor with implant alignment spacers includes a gate stack comprising a first nitride layer. The first nitride layer is formed on a silicon layer. The gate stack is separated from a substrate by a first oxide layer. The gate stack includes a polysilicon layer formed from the silicon layer, and a second oxide layer is formed on a sidewall of the polysilicon layer. A drain region of the LDMOS transistor is implanted with a first implant aligned to a first edge formed by the second oxide layer. A second nitride layer conformingly covers the second oxide layer. A nitride etch-stop layer conformingly covers the second nitride layer.

Abstract: A wearable safety apparatus including a body area network (BAN) transceiver for communicating with a user-controlled apparatus is described. The BAN transceiver includes a processor coupled to a BAN antenna. The processor is configured to receive an identification data request from a user-controlled apparatus in response to an action request of a user of the wearable safety apparatus; and to transmit identification data to the user-controlled apparatus in response to the identification data request. The identification data validates the user action by the user-controlled apparatus. The identification data request is only received when the wearable safety apparatus and the user-controlled apparatus are in contact with the user.

Abstract: A margin sensing circuit coupled to a flip flop of a critical data path includes a delay generator, a selector circuit which selects a delayed data output from the delay generator, a shadow latch corresponding to the flip flop, a comparator circuit which provides a match error indicator based on a comparison between a latched data output from the flip flop and a latched shadow output from the shadow latch, and an error latch to provide an error indicator based on the match error indicator. A correcting circuit includes a clock delay generator configured to receive a clock and provide a plurality of delayed clocks, and a clock selector circuit to select a delayed clock of the plurality of delayed clocks based on a set of clock select signals, in which each of the flip flop and the shadow latch are clocked by the selected delayed clock.

Abstract: A switching device may include an input terminal, an output terminal, a primary switching transistor coupled between the input terminal and the output terminal, logic circuitry configured to receive a control signal to selectively activate the switching device, a first cascode arrangement coupled between the logic circuitry and a first reference voltage supply, and a second cascode arrangement coupled between the input terminal and the primary switching transistor. The first cascode arrangement may include cascode transistors having gate terminals coupled to a first voltage divider coupled between the first reference voltage supply and a second reference voltage supply that is coupled to the logic circuitry. The second cascode arrangement may include a first cascode transistor coupled to a fixed voltage at the first voltage divider and second and third cascode transistors coupled to variable cascode bias voltages at a second voltage divider coupled to a variable voltage input.

Abstract: In an embodiment, a System-on-Chip (SoC) may include: a plurality of core domains, and a memory coupled to the plurality of core domains through a hardware firewall, wherein the hardware firewall is configured to enforce an adaptive Deny-By-Default (DBD) access policy in response to an event. In another embodiment, a circuit, may include: an access control policy generator configured to produce an adaptive DBD policy, and a hardware firewall coupled to the access control policy generator, the hardware firewall configured to enforce the adaptive DBD policy. In yet another embodiment, a method may include: storing an indication of a first DBD configuration state, the first DBD configuration state usable to enforce a first DBD access control policy, and changing the stored indication to a second DBD configuration state, the second DBD configuration state usable to enforce a second DBD access control policy.

Abstract: Systems and methods for resolving data (DQ) line swapping configuration in Double Data Rate (DDR) memories are described. In an illustrative, non-limiting embodiment, a system may include a memory controller and a memory coupled to the memory controller, the memory having program instructions stored thereon that, upon execution, cause the system to: apply a first technique to resolve DQ line swapping between a memory interface and a memory module with respect to a first subset of a plurality of DQ lines; apply a second technique different than the first technique to resolve DQ line swapping with respect to a second subset of the plurality of DQ lines; and apply a third technique different than the first and the second techniques to resolve DQ line swapping with respect to a third subset of the plurality of DQ lines.

Abstract: There is described a method of controlling a single inductor multiple output, SIMO, switching converter, the method comprising (a) counting, for each output of the multiple outputs of the SIMO switching converter, a period of time during which an output voltage at the respective output is below a corresponding individual threshold value, (b) identifying that output among the multiple outputs of the SIMO switching converter for which the counted period of time is longest, and (c) connecting the identified output to the single inductor of the SIMO switching converter to supply current from the single inductor of the SIMO switching converter to the identified output. Furthermore, a corresponding controller is described.

Abstract: A method of manufacturing a packaged semiconductor device is provided. The method includes placing a plurality of semiconductor die on a carrier substrate. The plurality of semiconductor die and an exposed portion of the carrier substrate are encapsulated with an encapsulant. A cooling fixture includes a plurality of nozzles and is placed over the encapsulant. The encapsulant is cooled by way of air exiting the plurality of nozzles. A property of air exiting a first nozzle of the plurality of nozzles is different from that of a second nozzle of the plurality of nozzles.