Patents Assigned to NXP
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Patent number: 10681679Abstract: A method for identifying active resource units in a high-efficiency wireless system includes quantizing phase angles of samples received in a high-efficiency short training field of a transmission, performing a transform operation on quantized phase angle samples to derive transmitted power, comparing transmitted power of an individual resource unit as determined from transformed quantized phase angle samples to transmitted power of other resource units as determined from transformed quantized phase angle samples, and identifying, as active, resource units whose transmitted power, as determined from transformed quantized phase angle samples, bears a first predetermined relationship to transmitted power of the other resource units. Transmitted power of a resource unit may be compared to the total transmitted power of all resource units, or to the transmitted power of one of the other resource units whose transmitted power is a maximum transmitted power of all resource units.Type: GrantFiled: June 11, 2018Date of Patent: June 9, 2020Assignee: NXP USA, Inc.Inventors: Xilin Cheng, Bo Yu, Xiayu Zheng
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Patent number: 10680572Abstract: Aspects of the disclosure are directed to auto-sweeping impedance-matching circuitry that matches an impedance of an RF antenna. As may be implemented in accordance with one or more embodiments, a transmitter that is configured and arranged to transmit signals to remote devices via the RF antenna, is used to communicate a plurality of test signals to the impedance-matching circuitry, with each test signal having a designated frequency and/or test signal pattern that is different than the designated frequency and/or test signal pattern of the other test signals. A characteristic of each of the test signals as passed through the impedance-matching circuitry is detected. For each of the test signals generated for the auto-sweep, the detected characteristic is compared to an expected characteristic for the test signal, and an output indicative of compliance of the impedance-matching circuitry with a design specification is generated and transmitted in response to the comparison.Type: GrantFiled: August 31, 2017Date of Patent: June 9, 2020Assignee: NXP B.V.Inventors: Gernot Hueber, Leonhard Kormann, Ian Thomas Macnamara
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Patent number: 10678920Abstract: According to a first aspect of the present disclosure, an electronic device is provided, comprising: an attack detection unit arranged to detect one or more attacks on the electronic device; a countermeasure unit arranged to apply countermeasures against the attacks detected by the attack detection unit; a threat level determination unit arranged to determine a threat level corresponding to the attacks detected by the attack detection unit; wherein the countermeasure unit is further arranged to activate one or more specific ones of said countermeasures in dependence on the threat level determined by the threat level determination unit. According to a second aspect of the present disclosure, a corresponding method of protecting an electronic device is conceived. According to a third aspect of the present disclosure, a corresponding computer program product is provided.Type: GrantFiled: March 31, 2017Date of Patent: June 9, 2020Assignee: NXP B.V.Inventor: Sebastian Stappert
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Patent number: 10680810Abstract: A method is provided for generating an elliptic curve cryptography key pair that uses two topologically identical pseudo-random number generators operating in parallel and in step with each other. One generator operates in the scalar number domain and the other generator operates in the elliptic curve point domain. Parallel sequences of pseudo-random elliptic curve points aG and corresponding scalars a are generated in this manner. A scalar a becomes a private key and an elliptic curve point aG is a public key of a key pair. Each generator is advanced by one iteration successively, and the isomorphic relationship ensures that the point domain generator always contains values which are multiples of the system base point according to values contained in the corresponding position in the number domain generator. In one embodiment, the pseudo-random number generators are each characterized as being lagged Fibonacci generators.Type: GrantFiled: October 26, 2016Date of Patent: June 9, 2020Assignee: NXP B.V.Inventors: Joppe Willem Bos, Bjorn Fay, Bruce Murray
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Patent number: 10673388Abstract: A bias circuit for a bipolar RF amplifier is described. The bias circuit includes a current source coupled to a bias network. The bias network supplies a base current to the transistors in the amplifier circuit of the bipolar RF amplifier. The bias circuit includes a buffer coupled to the bias network and to the bipolar RF amplifier. The buffer provides additional base current to the amplifier circuit of bipolar RF amplifier and sinks avalanche current generated by the amplifier circuit of the bipolar RF amplifier.Type: GrantFiled: September 14, 2018Date of Patent: June 2, 2020Assignee: NXP B.V.Inventors: Mark Pieter Van Der Heijden, Gerben Willem De Jong, Xin Yang
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Patent number: 10672903Abstract: A semiconductor device includes a drain region for a transistor, a drain active area directly below the drain region, a drift area directly below an insolation structure, and an accumulation area directly below a gate structure of the transistor. The semiconductor device includes a first selectively doped implant region of a first concentration of a first conductivity type extending to a first depth. The first selectively doped implant region is located in the drift area, the drain active area, and the accumulation area. The semiconductor device includes a second selectively doped implant region of a second concentration of the first conductivity type and extending to a second depth less than the first depth. The second concentration is less than the first concentration. The second selectively doped implant region is located the drain active area, but not in the accumulation area.Type: GrantFiled: July 25, 2018Date of Patent: June 2, 2020Assignee: NXP USA, INC.Inventors: Xin Lin, Saumitra Raj Mehrotra, Ronghua Zhu
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Patent number: 10673476Abstract: This disclosure describes a receiver having equalization with noise de-whitening mitigation for wireless communication. An input port receives, via an antenna, a signal communicated over a wireless communication link, the signal comprising a noise component. Control circuitry performs zero forcing equalization of the received signal to generate a zero forcing equalization result signal. The zero forcing equalization causes de-whitening of the noise component by increasing a correlation among elements of the noise component. The control circuitry mitigates the de-whitening of the noise component by: determining a noise variance value based on channel properties of the wireless communication link, and modifying the zero forcing equalization result signal based on the noise variance value. The modified zero forcing equalization result signal is communicated, via an output port, to log-likelihood ratio (LLR) generation circuitry for LLR computation.Type: GrantFiled: April 11, 2019Date of Patent: June 2, 2020Assignee: NXP USA, Inc.Inventors: Sayak Roy, Salil Kashyap, Ankit Sethi, Sudhir Srinivasa
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Patent number: 10673386Abstract: An amplifier may include a transistor and input and output matching networks. One or more harmonic trap circuits may be electrically connected to a node located between the input matching network and a gate terminal of the transistor or to a node located between the output matching network and a drain terminal of the transistor. Each harmonic trap may provide a low resistance path to ground for signal energy above a fundamental operating frequency of the amplifier, such as harmonic frequencies thereof. The output matching network may act as an impedance inverter that provides a 90 degree insertion phase between the input of the output matching network and the load. A variable length drain feeder may connect a voltage source to an output of the output matching network.Type: GrantFiled: December 5, 2017Date of Patent: June 2, 2020Assignee: NXP USA, Inc.Inventors: Roy McLaren, Ramanujam Srinidhi Embar
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Patent number: 10673387Abstract: An amplifier package may include a transistor, an output impedance matching circuit and one or more radial stub harmonic traps coupled to a control terminal of the transistor or to an output terminal of the transistor. The output impedance matching circuit and the radial stub harmonic traps may be formed on a single substrate or separate substrates, which may be formed from gallium nitride. Each radial stub harmonic trap may provide a low resistance path to ground for signal energy above a fundamental operating frequency of the amplifier, such as harmonic frequencies thereof.Type: GrantFiled: December 5, 2017Date of Patent: June 2, 2020Assignee: NXP USA, Inc.Inventors: Ramanujam Srindhi Embar, Roy McLaren
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Patent number: 10670425Abstract: A system for determining angular position includes a dipole magnet having an axis of rotation, wherein the dipole magnet produces a magnetic field. A first magnetic field sensor produces a first output signal and a second magnetic field sensor produces a second output signal in response to the magnetic field. The magnetic field sensors are operated in a saturation mode in which the magnetic field sensors are largely insensitive to the field strength of the magnetic field. Thus, the first output signal is indicative of a first direction of the magnetic field and the second output signal is indicative of a second direction of the magnetic field. Methodology performed by a processing circuit entails combining the first and second output signals to obtain a rotation angle value of the magnet in which angular error from a stray magnetic field is substantially cancelled.Type: GrantFiled: March 30, 2018Date of Patent: June 2, 2020Assignee: NXP B.V.Inventors: Jaap Ruigrok, Edwin Schapendonk, Marijn Nicolaas van Dongen
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Patent number: 10672703Abstract: A transistor includes a semiconductor substrate having an active device region formed therein and an interconnect structure on a first surface of the semiconductor substrate. The interconnect structure is formed of multiple layers of dielectric material and electrically conductive material. Drain and gate runners are formed in the interconnect structure. A shield structure extends above a second surface of the interconnect structure, the shield structure being positioned between the drain and gate runners.Type: GrantFiled: September 26, 2018Date of Patent: June 2, 2020Assignee: NXP USA, Inc.Inventors: Vikas Shilimkar, Kevin Kim, Hernan Rueda, Humayun Kabir
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Patent number: 10673547Abstract: Aspects of the disclosure provide an apparatus for wireless communication. The apparatus includes a transceiver and a processing circuit. The transceiver is configured to transmit and receive wireless signals. The processing circuit is configured to determine a transmission parameter adjustment for the transceiver, detect that the transmission parameter adjustment has a potential to cause a collision to an overlapping basic service set (OBSS), adjust timings for transmission control to avoid the collision, and control the transceiver based on the determined transmission parameter adjustment and the adjusted timings for transmission control.Type: GrantFiled: November 12, 2018Date of Patent: June 2, 2020Assignee: NXP USA, Inc.Inventors: Liwen Chu, Lei Wang, Jinjin Jiang, Hongyuan Zhang, Hui-Ling Lou
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Patent number: 10670699Abstract: Embodiments are provided for a radar device and a method for operating a radar device, the radar device having a transmitter and a receiver, the method including: generating a noise signal; mixing the noise signal with a transmitter output radio frequency (RF) signal to produce an intermediate signal, wherein the transmitter output RF signal is a version of a local oscillator (LO) signal having linearly increasing frequency; attenuating the intermediate signal to produce a test signal; adding the test signal to a receiver input RF signal to produce a combined receiver input RF signal; downmixing an amplified version of the combined receiver input RF signal with the LO signal to produce a combined low frequency signal; and correlating the combined low frequency signal with the noise signal to produce an error detection signal.Type: GrantFiled: September 7, 2017Date of Patent: June 2, 2020Assignee: NXP B.V.Inventors: Jan-Peter Schat, Abdellatif Zanati
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Patent number: 10673435Abstract: A method and apparatus for reducing dynamic switching current in high speed logic. The apparatus may include a CMOS logic circuit, which in turn includes an NMOS FinFET, a first PMOS FinFET, and a second PMOS FinFET. A gate of the NMOS FinFET is connected to a gate of the first PMOS FinFET, a drain of the NMOS FinFET is connected to a drain of the first PMOS FinFET, and the second PMOS FinFET is connected to the first PMOS FinFET to create a capacitor between a source and the drain of the first PMOS FinFET. In one embodiment, the second PMOS FinFET is contained in and positioned at an edge of a cell that also contains the first PMOS FinFET and the NMOS FinFET.Type: GrantFiled: October 31, 2018Date of Patent: June 2, 2020Assignee: NXP USA, INC.Inventors: Emmanuel Chukwuma Onyema, David Russell Tipple
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Patent number: 10672902Abstract: A field effect device includes a semiconductor body separating a source and a drain, both source and drain coupled to the semiconductor body. An insulated control gate is located over the semiconductor body between the source and drain and configured to control a conductive channel extending between the source and drain. First and second doped regions such as highly-doped regions are adjacent to the source. The first or second doped region may be a cathode short region electrically coupled to the source. The cathode short region may be used in a bidirectional power MOSFET.Type: GrantFiled: April 8, 2019Date of Patent: June 2, 2020Assignee: NXP USA, Inc.Inventors: Tanuj Saxena, Vishnu K. Khemka, Raghu Gupta, Moaniss Zitouni, Ganming Qin
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Patent number: 10667175Abstract: Embodiments described herein provide a method for fragmenting and reassembling data frames on a medium access control (MAC) layer in a wireless local area network. A datagram is received from an application running on a first network device, for transmission over a wireless communication link in the wireless local area network. A negotiation request is initiated with a second network device for determining whether both the first network device and the second network device have enhanced directional multi-gigabit capability (EDMG) for data segmentation and reassembly. When both devices have EDMG capability and the size of the datagram exceeds the maximum size defined by the wireless local area network transmission protocol, the datagram is segmented into a plurality of transmission data units on the MAC layer.Type: GrantFiled: March 9, 2018Date of Patent: May 26, 2020Assignee: NXP USA, Inc.Inventors: Jinjing Jiang, Liwen Chu, Hongyuan Zhang, Hui-Ling Lou
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Patent number: 10666303Abstract: Spurious signals are cancelled in a radio frequency (RF) transmitter. According to one method, a first baseband signal is fed into a first input port of an RF mixer of the RF transmitter, a carrier signal is fed into a second input port of the RF mixer, and an RF spurious signal is measured at an output port of the RF mixer. A baseband compensation signal is generated based on the first baseband signal and the RF spurious signal, and a modified baseband signal is generated by subtracting the baseband compensation signal from the first baseband signal. The modified baseband signal, instead of the first baseband signal, is fed into the first input port of the RF mixer.Type: GrantFiled: October 30, 2018Date of Patent: May 26, 2020Assignee: NXP USA, Inc.Inventors: Vijay Ahirwar, Nilesh Khude
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Patent number: 10661082Abstract: One example discloses a noninvasive biological conditioning device, including: a first induction structure; a second induction structure; a barrier configured to block direct contact between the structures and a material; wherein the structures are configured to induce an electrical current in the material; and wherein the electrical current is configured to have a set of attributes for conditioning biological activity in the material.Type: GrantFiled: October 31, 2017Date of Patent: May 26, 2020Assignee: NXP B.V.Inventor: Anthony Kerselaers
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Patent number: 10659013Abstract: A start-up circuit for a ring current-controlled oscillator (CCO) includes a replica CCO current generator, a replica ring CCO, and a buffer. The ring CCO is connected to a CCO driver and the buffer. The CCO driver generates a CCO current based on a reference current. The ring CCO generates a CCO output voltage at a first oscillating frequency based on the CCO current. The replica CCO current generator generates a replica CCO current based on a reference voltage. The replica ring CCO generates a replica CCO output voltage at a second oscillating frequency based on the replica CCO current. The buffer provides a first current to the ring CCO when the first oscillating frequency is lower than a desired oscillating frequency, and drains a second current from the ring CCO when the first oscillating frequency is greater than the desired oscillating frequency.Type: GrantFiled: January 1, 2019Date of Patent: May 19, 2020Assignee: NXP USA, Inc.Inventors: Yang Wang, Jianzhou Wu, Jie Jin, Jiawei Fu
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Patent number: 10658927Abstract: Regulation systems and methods use a first regulator and a tracking second regulator. The first regulator receives a reference voltage and generates a first voltage output based upon the reference voltage, which is coupled as a back-bias voltage to a first load region within the integrated circuit. The first regulator also receives a sampled version of the first voltage output as feedback. A second regulator receives the first sampled voltage output and generates a second voltage output. The second regulator also receives a sampled version of the second voltage output as feedback. During operation, the second voltage output tracks (e.g., by a symmetry ratio) the first voltage output and is coupled as a back-bias voltage to a second load region within the integrated circuit. Further, switched-capacitor operation can be implemented, and clock frequency can be adjusted based upon the first sampled voltage output to reduce power consumption.Type: GrantFiled: April 30, 2019Date of Patent: May 19, 2020Assignee: NXP USA, Inc.Inventors: Marcos Mauricio Pelicia, Ricardo Pureza Coimbra, Luis Enrique Del Castillo, Lei Tian