Abstract: Embodiments described herein methods and systems for channel correlation based user detection in an uplink multiuser transmission of a multiple-input multiple-output (MIMIO) network. In some embodiments, the channel correlation based user detection may be used in 802.11 UL MUMIMO systems. For example, an access point may detect whether a client station responds to a trigger frame and then adjust a channel matrix accordingly to reflect whether the client station is responsive. The access point may then decode received data signals based on the adjusted channel matrix that reflects whether a client station has transmitted.

Abstract: A receiver includes at least a first amplifier configured to receive a received signal and provide a first amplified signal based thereon, a mixer configured to receive the first amplified signal and provide an intermediate frequency signal based thereon and a second amplifier configured to receive the intermediate frequency signal and provide a second amplified signal based thereon. An automatic gain controller for the receiver is configured to, based on a first overload signal indicative of a first frequency range of the first amplified signal having one or more frequency components exceeding a first maximum signal power threshold and a second overload signal indicative of a second frequency range, narrower than the first, of the second amplified signal having one or more frequency components exceeding a second maximum signal power threshold, provide for control of a respective gain of one or both of the first amplifier and the second amplifier.

Abstract: Some embodiments described herein provide a method for transmitting a preamble in accordance with a wireless local area network communication protocol. In some embodiments, a data frame may be obtained for transmission including a preamble compliant with the wireless local area network communication protocol. It may be determined that the preamble includes a first preamble portion that spans multiple symbol durations and a second preamble portion that spans a single symbol duration. The first preamble portion via beamforming may be transmitted based on a first beamforming matrix. When a transmission mode of the second preamble portion is beamforming, a second beamforming matrix may be generated based on the first beamforming matrix, each tone for the second preamble portion may be calculated based on the second beamforming matrix. Each calculated tone may be transmitted in accordance with the wireless local area network communication protocol.

Abstract: An ESD protection device for protecting an integrated circuit against an ESD event includes a first terminal coupled to an input/output pad of the IC, a second terminal coupled to a reference or ground voltage, a silicon-controlled rectifier device having an anode connected to the first terminal and a cathode connected to the reference or ground voltage, and a pnp transistor coupled in parallel with the SCR device. The pnp transistor has an emitter coupled to the first terminal, a collector coupled to the second terminal, and a base coupled to a gate of the SCR. The pnp transistor includes a contact region formed at a first side of a substrate, the first contact region being surrounded by an STI layer formed at the first side of the substrate. An insulation structure is formed at an intersection of the first contact region and the STI layer.

Abstract: A processing engine for classifying data according to a decision tree having n-nodes is disclosed, wherein each node is represented by a respective test according to which a flag may be set or unset, comprising: a respective test unit and corresponding to each node, having an output flag and being configured to set or unset the respective output flag according to an output of the respective test; a memory configured to hold an n-bit word, each bit corresponding to a one of the respective output flags; and a data-structure configured as a look up table, each entry of the look up table representing a class of the data. Corresponding methods are also disclosed, as are devices and systems incorporating such processing engines.

Abstract: A first set of orthogonal frequency domain multiplexing (OFDM) symbols for a first portion of a PHY data unit and a second set of OFDM symbols for a second portion of the PHY data unit are generated. OFDM symbols of the first set are generated with a first OFDM tone spacing. At least some OFDM symbols of the second set are generated with a second tone spacing different from the first tone spacing. A value for a length indicator indicative of a duration of the PHY data unit is determined based on the first tone spacing and the second tone spacing. The first portion of the PHY data unit is generated to include (i) the first set of OFDM symbols and (ii) the length indicator set to the determined value. The second portion of the PHY data unit is generated to include the second set of OFDM symbols.

Abstract: One example discloses an interface circuit, including: an inductive coil having a first, second and third terminal; wherein the first terminal is coupled to an external interface port; wherein the second terminal is coupled to a first communication port; wherein the third terminal is coupled to a second communication port; and wherein the inductive coil is configured to attenuate an equivalent capacitance from at least one of the terminals.

Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.

Abstract: The present disclosure includes systems and techniques relating to multi-antenna coherent combining (MACC) for carrier sensing (CS) and symbol timing (ST) in a wireless communication system. In some implementations, a device includes a receiver and processor electronics. The receiver is configured to receive two or more signals from two or more antennas, each of the two or more signals including a known, periodic reference signal that has gone through a respective wireless channel via one of the two or more antennas. The processor electronics are configured to obtain estimated phases of the two or more signals from the two or more antennas; obtain a combined signal by combining the two or more signals with coherent estimated phases of the two or more signals; and perform carrier sensing and symbol timing of the two or more signals based on the combined signal.

Abstract: A method of obscuring the input and output of a modular exponentiation function, including: receiving modular exponentiation parameters including an exponent e having N bits and a modulus m; generating randomly a pre-multiplier; calculating a post-multiplier based upon the pre-multiplier, exponent e, and modulus m; multiplying an input to the modular exponentiation function by the pre-multiplier; performing the modular exponentiation function; and multiplying the output of the modular exponentiation function by the post-multiplier, wherein multiplying an input to the modular exponentiation function by the pre-multiplier, performing the modular exponentiation function, and multiplying the output of the modular exponentiation function by the post-multiplier are split variable operations.

Abstract: A method, system, and apparatus are provided for preventing glitch attacks by using a glitch processing hardware unit (1) to deactivate a glitch filter connected between the monitored line and a reset processing unit in response to detecting a voltage glitch on a monitored line during a specified security system sequence and (2) to automatically drive a requested reaction in response to the voltage glitch by driving one of a plurality of configurable reactions comprising a device reset reaction and a process restart request, thereby preventing the voltage glitch from maliciously influencing the specified security system sequence.

Abstract: A semiconductor apparatus includes a first device cell and a second device cell. The first device cell includes a first active region including a first set of device fins, an insulator layer disposed over the first set of device fins, a first gate fin over the first set of fins, and a first edge fin disposed over a first edge of the first active region. The second device cell is adjacent the first device cell and includes a second active region including a second set of device fins, the insulator layer disposed over the second set of device fins, a second gate fin over the second set of device fins, and a second edge fin disposed over a second edge of the second active region. The first edge fin and the second edge fin are connected to a power rail, a ground rail, or to each other to define a capacitor between the first device cell and the second device cell.

Abstract: A tamper detection device includes a detection circuit, configured to be powered by a near-field-communication (NFC) signal and store a status of a detection element; wherein the detection circuit is configured to set the status to undisturbed in response to an undisturbed state of the detection element; wherein the detection circuit is configured to set the status to disturbed in response to a disturbed state of the detection element; and wherein the detection circuit is configured to electrically report the detection element status in response to a wireless query signal.

Abstract: Consistent with an example embodiment, there is a package assembly structure. The structure comprises a lead frame having a topside surface and an opposite under-side surface; the lead frame includes a die attach paddle, wherein a die attach region is defined on the opposite under-side surface. Pad landings surround the die attach region. A plurality of locking pins are arranged at predetermined locations about the die attach paddle, on the top side surface. The plurality of locking pins may be formed integrally in the lead frame and project upward from the top side surface.

Abstract: The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

Abstract: A low voltage bandgap reference circuit (200) is provided which includes a first current generator (202) having first and second circuit branches which include, respectively, first and second bipolar transistors having different sizing reference values for generating a first current at a first resistor that varies proportionally as a function of temperature; a second current generator (204, 205) having a third circuit branch which includes one or more field effect transistors and no bipolar transistors for generating a second current that varies inversely as a function of temperature; and a third circuit (206) connected to generate a bandgap reference current in response to the first current and the second current.

Abstract: Embodiments provide forced-burst voltage regulation for burst mode direct-current-to-direct-current (DC-DC) converters in integrated circuits. The DC-DC converter generates an output voltage and operates in a burst mode to raise the output voltage to a threshold voltage. A controller is coupled to the DC-DC converter. In operation, the DC-DC converter is configured to perform the burst mode based upon a low-voltage detection for the output voltage. The DC-DC converter is further configured to perform the burst mode when a force-burst command is asserted by the controller to the DC-DC converter regardless of a state for the low-voltage detection. For one embodiment, the force-burst command is asserted as a burst control signal from the controller to the DC-DC converter to generate a long quiet period for sensitive actions. For another embodiment, the force-burst command is asserted using enable and refresh control signals to facilitate low-power operation.

Abstract: A magnetic field sensor includes a magnetic sense element and a shield structure formed on a substrate. The shield structure fully encircles the magnetic sense element for suppressing stray magnetic fields along a first axis and a second axis, both of which are parallel to a surface of the substrate and perpendicular to one another. A magnetic field is oriented along a third axis perpendicular to the surface of the substrate, and the magnetic sense element is configured to sense a magnetic field along the first axis. A magnetic field deflection element, formed on the substrate proximate the magnetic sense element, redirects the magnetic field from the third axis into the first axis to be sensed as a measurement magnetic field by the magnetic sense element. At least two magnetic field sensors, each fully encircled by a shield structure, form a gradient unit for determining a magnetic field gradient.

Abstract: A processor scheduling structure, a method and an integrated circuit are provided. In accordance with at least one embodiment, the processor scheduling structure comprises a processor circuit and an operating system task aware caching (OTC) controller circuit coupled to the processor circuit. The OTC controller circuit comprises a load request timer, a load sequence queue (LSQ), and a request arbiter. The timer and the LSQ are coupled to and provide inputs to the request arbiter. The processor circuit comprises an internal memory and a processor core. The OTC controller circuit is configured to schedule processor tasks for the processor circuit in accordance with both priority-based scheduling, using the LSQ, and time-triggered scheduling, using the load request timer.

Abstract: Various embodiments relate to a key protocol exchange that provide a simple but still secure key exchange protocol. Security of key exchange protocols has many aspects; providing and proving all these properties gets harder with more complex protocols. These security properties may include: perfect forward secrecy; forward deniability; key compromise impersonation resistance; security against unknown key share attack; explicit or implicit authentication; key confirmation; protocol is (session-)key independent; key separation (different keys for encryption and MACing); extendable, e.g. against DOS attacks . . . (e.g. using cookies, . . . ); support of early messages; small communication footprint; and support of for public-key and/or password authentication.