Abstract: A processor scheduling structure, a method and an integrated circuit are provided. In accordance with at least one embodiment, the processor scheduling structure comprises a processor circuit and an operating system task aware caching (OTC) controller circuit coupled to the processor circuit. The OTC controller circuit comprises a load request timer, a load sequence queue (LSQ), and a request arbiter. The timer and the LSQ are coupled to and provide inputs to the request arbiter. The processor circuit comprises an internal memory and a processor core. The OTC controller circuit is configured to schedule processor tasks for the processor circuit in accordance with both priority-based scheduling, using the LSQ, and time-triggered scheduling, using the load request timer.

Abstract: Time-interleaved analog-to-digital converters (ADCs) and related methods are disclosed that are based upon multiplying digital-to-analog converters (MDACs). For one ADC embodiment, a sample-and-hold circuit receives an input signal and outputs a voltage that represents the input signal. An MDAC receives the voltage, outputs an N-bit digital value, and outputs a current that represents the voltage. A phased current generator receives the current and outputs time-interleaved currents that are based upon the current. An array of sub-ADCs receive the time-interleaved currents, and each sub-ADC outputs a digital value. The digital values from the array of sub-ADCs are then combined and to output an M-bit digital value. The N-bit digital value and the M-bit digital value provide a digital conversion output for the ADC.

Abstract: Embodiments of methods and systems for operating a communications device that communicates via inductive coupling are described. In an embodiment, a method for operating a communications device that communicates via inductive coupling involves obtaining at least one system or environmental parameter related to the communications device and adjusting a communications configuration of the communications device in response to the at least one system or environmental parameter. Other embodiments are also described.

Abstract: A method is provided for establishing a communication session in a communications system. The method includes providing a handshake layer functional block in a first communication peer, and providing a data communication layer functional block separate from the handshake layer functional block in the first communication peer. Functionality of the data communication layer is not duplicated in the handshake layer. If the data communication layer is unable to process a received encrypted message; transmitting, by the data communication layer, a configuration request message to the handshake layer, and transmitting, by the handshake layer, in response to the configuration request message, a set channel state message to enable the data communication layer to process application data after a handshake phase of the protocol session is complete. Then, application data can be communicated through the data communication layer functional block of the first communication peer to a second communication peer.

Abstract: Various embodiments relate to a key protocol exchange that provide a simple but still secure key exchange protocol. Security of key exchange protocols has many aspects; providing and proving all these properties gets harder with more complex protocols. These security properties may include: perfect forward secrecy; forward deniability; key compromise impersonation resistance; security against unknown key share attack; explicit or implicit authentication; key confirmation; protocol is (session-)key independent; key separation (different keys for encryption and MACing); extendable, e.g. against DOS attacks . . . (e.g. using cookies, . . . ); support of early messages; small communication footprint; and support of for public-key and/or password authentication.

Abstract: A method for performing a secure boot of a data processing system, and the data processing system are provided. The method includes: processing a command issued from a processor of the data processing system, the command directed to a memory; determining that the command is a command that causes the memory to be modified; performing cryptographic verification of the memory; and incrementing a first counter in response to the determining that the command is a command that causes the memory to be modified. The data processing system includes a processor, a memory, and a counter. The memory is coupled to the processor, and the memory stores data used by a bootloader during a secure boot. The counter is incremented by a memory controller in response to a command being a type of command that modifies the data stored by the memory.

Abstract: A magnetic field sensor includes a magnetic sense element and a shield structure formed on a substrate. The shield structure fully encircles the magnetic sense element for suppressing stray magnetic fields along a first axis and a second axis, both of which are parallel to a surface of the substrate and perpendicular to one another. A magnetic field is oriented along a third axis perpendicular to the surface of the substrate, and the magnetic sense element is configured to sense a magnetic field along the first axis. A magnetic field deflection element, formed on the substrate proximate the magnetic sense element, redirects the magnetic field from the third axis into the first axis to be sensed as a measurement magnetic field by the magnetic sense element. At least two magnetic field sensors, each fully encircled by a shield structure, form a gradient unit for determining a magnetic field gradient.

Abstract: Systems and methods for converting a capacitance signal into a band-limited voltage signal for improved signal processing are disclosed herein. Such systems can include a capacitance-to-voltage converter configured to convert a capacitive signal from a capacitive device that operates at a mechanical frequency into a raw voltage signal, a clock generator configured to convert the mechanical frequency into one or more clock signals, and a filter component configured to apply a band-pass filter response to the raw voltage signal to convert the raw voltage signal into a band-limited voltage signal. The clock generator can be configured to apply the one or more clock signals to the filter component to drive a first pole and a second pole of the band-pass filter response to track the mechanical frequency of the capacitive device such that the geometric mean of the first pole and the second pole is substantially equal to the mechanical frequency.

Abstract: A first communication device transmits a first physical layer protocol data units (PPDU) that includes a first null data packet announcement (NDPA) frame as part of a first ranging measurement exchange. The first communication device transmits a first null data packet (NDP) as part of the first ranging measurement exchange, and records a transmit time of the first NDP. The first communication device determines whether a second NDP was received correctly from a second communication device as part of the first ranging measurement exchange. In response to determining that the second NDP was not received correctly, the first communication device commences a second ranging measurement exchange, including transmitting a second PPDU that includes a second NDPA frame as part of the second ranging measurement exchange.

Abstract: A flexure for a MEMS device includes an elongated beam and a protrusion element extending outwardly from a sidewall of the elongated beam. A MEMS inertial sensor includes a movable element spaced apart from a surface of a substrate, an anchor attached to the substrate, and a spring system. The spring system includes first and second beams, a center flexure between the first and second beams, a first end flexure interconnected between an end of the first beam and the anchor, and a second end flexure interconnected between an end of the second beam and the movable element. Each of the end flexures includes the elongated beam having first and second ends, and the sidewall defining a longitudinal dimension of the elongated beam, and the protrusion element extending from the sidewall of the elongated beam, the protrusion element being displaced away from the first and second ends of the beam.

Abstract: A communication device receives a physical layer (PHY) protocol data unit (PPDU). The PPDU includes i) a PHY preamble and ii) PHY data portion that includes one or more PHY midambles, and the PHY preamble includes i) an indication of a length of the PPDU, and ii) an indication of a periodicity of PHY midambles in the PHY data portion. The communication device calculates a number of PHY midambles in the PPDU using i) the indication of the length of the PPDU, and ii) the indication of the periodicity of PHY midambles. The communication device calculates a reception time for the PPDU using the calculated number of PHY midambles, and processes the PPDU using the calculated reception time.

Abstract: A processing module for a receiver device. The processor module comprises a channel estimate generation component arranged to output channel estimate information for a received signal, and a timestamping module arranged to determine a ToA measurement for a marker within a packet of the received signal based at least partly on the channel estimate information for the received signal generated by the channel estimate generation component. The channel estimate generation component comprises a validation component arranged to derive a validation pattern for the packet within the received signal for which a ToA measurement is to be determined, identify a section of the packet containing a validation sequence, and perform cross-correlation between at least a part of the validation sequence within the packet and at least a part of the generated validation pattern to generate channel estimate validation information.

Abstract: A communication device generates a first portion of a physical layer (PHY) preamble of a PHY data unit to include a first plurality of orthogonal frequency division multiplexing (OFDM) symbols. Each OFDM symbol of the first plurality of OFDM symbols is modulated on at most X OFDM subcarriers, where X is a positive integer greater than one. The communication device generates a second portion of the PHY preamble to include a second plurality of OFDM symbols. Each OFDM symbol of the second plurality of OFDM symbols is modulated on at most N*X OFDM subcarriers, where N is a positive integer greater than one. The communication device generates a PHY data portion of the PHY data unit to include one or more third OFDM symbols. Each third OFDM symbol is modulated on at most N*X OFDM subcarriers. The communication device transmits the PHY data unit via the wireless communication channel.

Abstract: A sensor may include: a first plurality of resistors; a first BJT having: a first base terminal, a collector terminal, and an emitter terminal, where the collector terminal is coupled to the first plurality of resistors; and a first amplifier having a first non-inverting input coupled to the collector terminal and an output terminal coupled to the base terminal. The sensor may include: a second plurality of resistors; a second BJT having: a base terminal, a collector terminal, and an emitter terminal, where the base terminal is coupled to the base terminal of the first BJT, where the collector terminal is coupled to the second plurality of resistors; and a second amplifier having an inverting input coupled to the collector terminal and an output terminal coupled to the emitter terminal, wherein the inverting input terminal of the first amplifier is coupled to a non-inverting input terminal of the second amplifier.

Abstract: The present application relates to a sub-bandgap reference source circuit, which comprises a current mirror source, a first branch comprising a first BJT and a second branch comprising a second BJT, the first BJT having an emitter current density lower than an emitter current density of the second BJT, the first branch and the second branch being connected at a first node coupled to ground; a first voltage divider comprising first and second resistances coupled in series, the first resistance being coupled between a base terminal of the first BJT and a second node, the second resistor being coupled to ground; a second voltage divider comprising first and second resistances coupled in series, the first resistance being coupled between the second node and a base terminal of the second BJT, the second resistance being coupled to the first node; and an output terminal coupled to the second node.

Abstract: The present application relates to an apparatus and method of authenticating and verifying a message frame on a multi-master access bus with message broadcasting. Logic bus identifier, LID, are associated with each one of a several logical groups of nodes out of a plurality of nodes connected to the multi-master access bus. A key is assigned to each logical group. The keys assigned to different logical groups differ from each other. For message authentication, a logic bus identifier, LID is provided and a key associated with the logic bus identifier, LID, is retrieved. A cryptographic hash value, MAC, is generated using the retrieved key and based on at least the logic bus identifier, LID. A message frame is composed, which comprises the logic bus identifier, LID, and the cryptographic hash value, MAC. For message verification, a message frame is received, which comprises at least a logic bus identifier, LID, and a cryptographic hash value, MAC.

Abstract: A data-processing-circuit comprising: a clock-input-terminal configured to receive a clock-signal; a data-output-terminal configured to provide a data-output-signal; an adjustable-driver-buffer configured to: receive a data-signal; and apply a driver-strength-value to the data-signal in order to provide a data-output-signal, wherein the current level of the data-output-signal is based on the driver-strength-value; and a driver-control-module comprising: a time-alignment-module configured to: process the clock-signal and the data-output-signal in order to determine a timing-delay-signal that is representative of a time delay between: a transition in the clock-signal; and a transition in the data-output-signal; provide the driver-strength-value for the adjustable-driver-buffer based on the timing-delay-signal and a target-delay-signal, wherein the driver-strength-value is for reducing a difference between: the timing-delay-signal; and the target-delay-signal.

Abstract: One example discloses a liquid exposure sensing device, including: a first sensor configured to be coupled to a reference material; wherein the first sensor configured to generate a first signal in response to either a liquid phase and/or vapor phase of a substance passing through the reference material; a second sensor configured to be coupled to an exposed material; wherein the second sensor configured to generate a second signal in response to the liquid phase and/or vapor phase of the substance passing through the exposed material; and a controller coupled to the first and second sensors and configured to generate a liquid detection signal in response to a time delay between the first signal and the second signal that exceeds a threshold time delay.

Abstract: A clock generator that generates an output clock signal, includes a clock generating circuit that generates an internal clock signal, first and second filter circuits, and an output gate. The first filter circuit receives the internal clock signal and an enable signal, and provides a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the clock signal. The second filter circuit receives the first filtered enable signal, provides a second filtered enable signal in response to the first filtered enable signal, and provides a delayed signal that is a delayed version of the second filtered enable signal. The output gate receives the internal clock signal from the clock generating circuit and the second filtered enable signal from the second filter circuit, and generates the output clock signal.

Abstract: An integrated “pull-down” driver circuit (210) is formed with a combination device consisting of an output driver transistor (N1) electrically coupled between a current source circuit (Ns) and the conductive pad, and an ESD bypass transistor (N3) electrically coupled in series with the output driver transistor, where one or more conductive interconnect layers connect the ESD bypass transistor in parallel with the current source circuit so that the ESD bypass transistor is in an off-state during normal operation and is activated to form a parasitic bipolar junction transistor with the output driver transistor to conduct ESD current between a first power supply conductor and the conductive pad during ESD events, and where a complementary integrated “pull-up” driver circuit may be formed with three corresponding PMOS transistors (P1, PS, P3) connected as shown between a second power supply conductor and the conductive pad.