Abstract: The embodiments described herein provide radio frequency (RF) amplifiers, and in some embodiments provide amplifiers that can be used in high power RF applications. Specifically, the amplifiers described herein may be implemented with multiple resonant circuits to provide class F and inverse class F amplifiers and methods of operation. In general, the resonant circuits are implemented inside a device package with a transistor die to provide high efficiency amplification for a variety of applications.

Abstract: A first communication device receives an indication that a second communication device permits a duplex transmission while the second communication device transmits during a transmit opportunity period (TXOP), where duplex transmissions involve simultaneously transmitting and receiving via a same wireless frequency band. The indication is included in a media access control layer (MAC) protocol data unit (MPDU). In response to receiving the indication that the second communication device permits the duplex transmission, the first communication device determines that the first communication device is permitted to perform the duplex transmission during the TXOP. The first communication device receives a first packet from the second communication device during the TXOP, and transmits a second packet while the first communication device is receiving the first packet.

Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an implant mask (81) to implant ions (91) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode (111) from contacting the peripheral edge and sidewalls of the mesa structures.

Abstract: A surge protection circuit includes a DC trigger circuit that generates a trigger signal when a surge pulse occurs, and a surge protection device, coupled to the DC trigger circuit, that generates a clamp voltage as an output voltage of the surge protection circuit and conducts surge currents to ground in response to the trigger signal. A feedback circuit is provided between the surge protection device and the DC trigger circuit. The feedback circuit lowers the clamp voltage so that it does not exceed a failure voltage of the surge protection device.

Abstract: A redriver powers up a high-speed channel within a time window sufficient to satisfy the requirements of a CIO mode of operation. The redriver includes a signal detector for a channel and control logic to activate the channel within a time window that satisfies operation in a CIO mode. The control logic may activate the channel by controlling a first bias current for a first circuit of the channel based on a signal detected by the signal detector. The first bias current may be greater than a second bias current for the first circuit during a mode different from the CIO mode. These features may form any linear or limiting redriver for a faster power-up time.

Abstract: A flexible semiconductor device includes a first tape having bonding pads and conductive traces formed. A semiconductor die having a bottom surface is attached to the first tape and electrically connected to the bond pads by way of electrical contacts. A second tape is attached to a top surface of the semiconductor die. The first and second tapes encapsulate the semiconductor die, the electrical contacts, and at least a part of the conductive traces.

Abstract: A semiconductor memory circuit includes a SRAM cell and a bias control circuit for biasing the SRAM cell. The SRAM cell includes pull-up, pull-down, and pass-gate transistors. The bias control circuit is connected to body terminals of the pull-down and pass-gate transistors for providing a bias voltage. The bias control circuit controls threshold voltages of the pull-down and pass-gate transistors by way of the bias voltage. The bias voltage, which is temperature dependent, is generated based on junction leakages at the body terminals of the pull-down and pass-gate transistors. The use of a temperature-dependent bias voltage to bias the body terminals of the pull-down and pass-gate transistors ensures that the write margin and the static noise margin (SNM) of the SRAM cell are relatively constant and above acceptable levels over a defined temperature range.

Abstract: A receiver is provided. The receiver includes a first signal path and a second signal path coupled between an input terminal and an output terminal. A first transistor in the first signal path has a control electrode coupled to a voltage source terminal and a first current electrode coupled at the input terminal. The first transistor is configured and arranged for receiving a first signal at the first input terminal having a voltage exceeding a voltage rating of the first transistor. A second transistor in the first signal path has a first current electrode coupled to a second current electrode of the first transistor and a control electrode coupled to receive a first control signal. The second transistor is configured to form an open circuit in the first signal path when the first control signal is at a first state. A first resistor network in the second signal path is configured and arranged for attenuating the first signal.

Abstract: A microelectromechanical systems (MEMS) device and a method for calibrating a MEMS device. The device includes a first semiconductor substrate including at least one MEMS component. The device also includes an application specific integrated circuit (ASIC) comprising a second semiconductor substrate. The second semiconductor substrate is attached to the first semiconductor substrate. The second semiconductor substrate includes at least one piezoresistive strain gauge. Each piezoresistive strain gauge includes at least one doped semiconductor region having a resistivity that is determined by a strain on said doped semiconductor region. The second semiconductor substrate also includes a circuit for evaluating a trim algorithm for the at least one MEMs component using one or more output values received from the at least one piezoresistive strain gauge.

Abstract: Various embodiments relate to a method of encrypting a message m using a Paillier cryptosystem, including: computing a ciphertext c based upon the message m, N, and r, where N is the product of two distinct primes p and q, and r is randomly chosen such that r?[1, N); computing a first verification value based upon u and N, where u is randomly chosen such that u?[1, N); computing a second verification value s based upon u, r, the ciphertext c, the verification value, and a hash function H.

Abstract: Within the EMV payment specification, the use of an unattended terminal to accept a payment is allowed. Creating a device that has both the EMV level 1 (L1) and level 2 (L2) payment components combined with a virtual merchant creates a “card present” transaction for an on-line or e-commerce merchant. This device can be called a personal Point of Sale (pPOS). This specification discloses personal Point of Sale (pPOS) devices and methods that can provide for card present e-commerce transactions. In some embodiments, a pPOS device can include only a secure microcontroller function (MCF), a payment kernel, a secure element, and an interface to an external system with an EMV level 3 (L3) payment application. In some embodiments, a pPOS device can further include a reader. In some embodiments, a pPOS device can still further include a sensor switch and/or a user interface function.

Abstract: An integrated circuit has a first gated diode with one or more diode fingers. Each diode finger has an elevated gate, an underlying p-type diffusion, and an underlying n-type diffusion. Each diffusion has a base region and an annular side region located between the base region and the elevated gate such that the diffusions have increased lateral surface areas that support greater current levels for the diode finger, which enables gated diodes to be implemented with fewer fingers and therefore less layout area than equivalent conventional gated diodes that do not have elevated gates. The first gated diode can be implemented with an analogous second gated diode to form ESD-protection circuitry for the integrated circuit.

Abstract: A read-only memory (ROM) includes ROM cells and a bias control circuit for biasing the ROM cells. Each ROM cell includes a set of transistors. The bias control circuit is connected to body terminals of the transistors of each ROM cell to provide a bias voltage. The bias voltage, which is temperature-dependent, is generated based on junction leakages at the body terminals of the transistors. The bias control circuit controls threshold voltages of the transistors using the bias voltage. The use of a temperature-dependent bias voltage to bias the body terminals of the transistors allows for a relatively constant read margin for each ROM cell.

Abstract: A comparator circuit includes a first transistor have a control electrode coupled to a first input voltage, a first current electrode coupled to a second input voltage, and a second current electrode coupled to a first circuit node. The circuit also includes a first inverter coupled to a first voltage supply terminal and having a first input coupled to the first circuit node and an output, a second transistor having a control electrode coupled to the output of the first inverter, and an active resistive element coupled in series between the first circuit node and a first current electrode of the second transistor.

Abstract: The present invention provides for a system that makes use of a system power supply enable switch controlled by a near field communications (NFC) frontend with energy harvesting. In one embodiment, RF power in the 13.56 MHz band generated by a NFC counterpart (such as a mobile phone) is detected by the energy harvesting unit being part of the battery-unpowered NFC communication device. After activation, the system can perform actions required to communicate to the presented device (i.e., the NFC counterpart). Later, the system can switch itself into the unpowered state again. In another embodiment, this feature can also be used to control an NFC protection circuitry very quickly after the NFC device is exposed to an external HF (high frequency) field.

Abstract: A secure computing device, including: a processor configured to carry out a secure operation; a memory in communication with the processer configured to store secure data; and a memory controller configured control storage of data in the memory and reading data from the memory, wherein the secure data is split into shares before being stored in the memory and wherein the memory controller is configured to: apply a masking storage transform (MST) to one of the shares to produce a masked share before storing the shares in the memory, wherein the MST is a permutation without a fixed point; apply an inverse MST to the masked share when reading the shares from the memory; and combine the read shares to reconstruct the secure data.

Abstract: Various embodiments relate to a method of hashing a message M using a block cipher, including: producing N block cipher inputs by XORing message indices i, . . . i+N?1 respectively with state values S0, . . . SN?1, wherein N is an integer greater than 1; producing N block cipher keys by XORing N different blocks of message M and at least one of state values S0, . . . SN?1 for each of the N block cipher keys; encrypting the N block cipher inputs using the respective N block cipher keys to produce N block cipher outputs; combining the N block cipher outputs with N block cipher inputs to produce N block cipher combined outputs Tt, for t=0, . . . , N?1; calculating Y0=T0; calculating Yt=Yt?1?Tt, for t=1, . . . , N?1, calculating SN?1?=YN?1<<<a, where a is a number of bits to rotate where S0?, . . . , SN?1? are new state values; and calculating St?=Yt?SN?1?, for t=0, . . . , N?2.

Abstract: A computing system using low-fat pointers, including: a memory configured to be accessed by the low-fat pointers; a processing core configured to access the memory; an interrupt controller configured to receive interrupts and to communicate interrupts to processes running on the processing core; and a memory safety peripheral configured to receive a pointer request, wherein the pointer is a low-fat pointer and to verify that the pointer request is within required memory bounds.

Abstract: This specification discloses methods and systems providing reader-mode performance enhancement for operating a device that communicates via inductive coupling. In reader-mode, Tx (transmitter) power of a reader device is maximized even though for some tags, the communication distance is limited by Rx (receiver) sensitivity. Therefore, power is wasted. Even worse, a too highly boosted Tx power demands a high Rx dynamic range and consequently a low Rx sensitivity. In turn, the communication distance may even be degraded by a too highly boosted Tx power. Therefore, in some embodiments, reader-mode performance enhancement is based on backing off Tx (transmitter) power when not needed (energy distance>communication distance) to save power and/or to relax reader-mode Rx (receiver) sensitivity requirements. In some embodiments, the backing off of Tx (transmitter) is also based on a sensor determining a geometric position/location of a reader device relative to a tag-mode device.

Abstract: A system includes a magnetic field sense element for detecting an external magnetic field and a magnetic field source proximate the magnetic field sense element for providing a reference magnetic field. The magnetic field sense element produces a composite signal having reference and measurement signal portions, the reference signal portion being indicative of the reference magnetic field and the measurement signal portion being indicative of the external magnetic field. A power supply provides a supply current through the magnetic field source for continuously generating the reference magnetic field while the system is in an operational mode. A processing circuit processes the composite signal to produce a measurement output signal indicative of the external magnetic field. A qualification circuit, coupled with the processing circuit at multiple test points, detects the reference signal portion at the multiple test points and determines operability of the system from the detected reference signal portion.