Abstract: Embodiments of a method, a device and a computer-readable storage medium are disclosed. In an embodiment, a method for operating a Controller Area Network (CAN) device involves in response to receiving bits of an arbitration field of a CAN data frame at the CAN device, selecting a timing engine from a plurality of timing engines and sampling subsequent bits of the CAN data frame using the selected timing engine. The timing engines have different sample clock frequencies.

Abstract: Methods and systems are disclosed herein for performing channel estimation for multi-stream packets. The method may include receiving a data packet comprising a plurality of training fields, wherein the plurality of training fields comprises a training field, wherein the training field comprises a plurality of tones, and wherein the plurality of tones comprises a first tone and a second tone. The method may include modifying the first tone based on a predetermined signal associated with the first tone. The method may include storing the first tone in a data structure associated with the first tone. The method may include modifying the data structure based on the second tone.

Abstract: An apparatus is configured to, based on a first signal comprising one or more data transmission frames received from a first radio device by a second radio device. The first signal has a particular carrier frequency of a carrier wave thereof and the one or more data transmission frames comprising a plurality of symbols provided at a particular symbol frequency. The carrier frequency and symbol frequency based on a reference clock frequency of the first radio device. One or more of an estimate of the particular carrier frequency is determined and an estimate of the particular symbol frequency relative to a reference clock frequency of the second radio device and provide for transmission of a response signal from the second radio device to the first radio device.

Abstract: A multi-beam-former for an antenna array is described, the multi-beam former comprises N transceiver terminals for connecting a transmitter and/or receiver and N antenna terminals for connecting to a respective antenna and a plurality of couplers and matrix phase shifters arranged in an N×N Butler matrix configuration between the N transceiver terminals and the N antenna terminals. At least some of the matrix phase shifters include a switchable matrix phase shifter configured to switch between a respective first phase shift value and a respective second phase shift value; a plurality of bypassable phase shifters arranged between at least some of the couplers and the antenna terminals and configured to switch between a respective further phase shift value and a zero phase shift. The multi-beam former is operable to select one of M different beam angles for a signal, wherein M is greater than N.

Abstract: A defrosting system includes an RF signal source, an electrode proximate to a cavity within which a load to be defrosted is positioned, and a transmission path between the RF signal source and the electrode. The system also includes power detection circuitry coupled to the transmission path and configured repeatedly to take forward and reflected RF power measurements along the transmission path. A system controller repeatedly determines, based on the forward and reflected RF power measurements, a calculated rate of change, and repeatedly compares the calculated rate of change to a threshold rate of change. When the calculated rate of change compares favorably with the threshold rate of change, the RF signal source continues to provide the RF signal to the electrode until a determination is made that the defrosting operation is completed, at which time the RF signal source ceases to provide the RF signal to the electrode.

Abstract: A device fabricated on a wafer is disclosed. The device includes a first block of the wafer and a second block of the wafer isolated from the first block using a first deep trench isolation (DTI). The device further includes a third block of the wafer isolated from the second block using a second DTI. The second block includes a first vertical section coupled to a first ground, a second vertical section, a third vertical section coupled to a second ground. The second vertical section is doped lightly compared to the first vertical section and the second vertical section.

Abstract: An integrated circuit package is described comprising an integrated circuit die and an antenna structure coupled to the integrated circuit die and comprising a stacked arrangement of metal and dielectric layers, wherein a first metal layer includes a planar antenna and at least one further metal layer comprises an artificial dielectric layer. The integrated circuit package may improve the directionality of the antenna and reduces the sensitivity of the antenna to the printed circuit board on which the integrated circuit package is mounted.

Abstract: A multi-band antenna suitable for use by vehicles has ports for Wi-Fi and DSRC signals, cellular signals, and GPS signals. A base substrate forms a ground plane, and a shark-fin shaped radiating substrate is transversely aligned with the base substrate. On a first side of the radiating substrate there is a first conductive feed strip with a vertical extending portion that is galvanically connected to the first port, and a second conductive feed strip that is galvanically connected to the second port. On a second side of the radiating substrate there is a first wide-slot that is capacitively coupled to the first and second feed strips, is galvanically connected to the base conductor, and overlaps with at least the extending-portion of the first feed strip. There also is a second wide-slot on the second side that extends from a back edge to a location between the first and second ports.

Abstract: Systems and methods described herein provides a method for dynamically allocating an iteration number for a decoder. The method includes receiving, at an input buffer, an input signal including at least one data packet. The method further includes calculating a first iteration number for decoding the at least one data packet. The method further includes monitoring at least one of available space of the input buffer and available decoding time for the at least one data packet. The method further includes dynamically adjusting the first iteration number to a second iteration number based on the available space or the available decoding time to continue decoding the at least one data packet.

Abstract: The invention provides a communications device which uses a clock circuit for generating a clock signal, the clock circuit comprising a tuneable oscillator. The clock frequency is varied to make sure it remains within a tolerance range, so that the device can continue to receive messages correctly. An error rate of received messages is determined, and in response to the error rate exceeding a threshold, a setting of the resistor arrangement and/or the capacitor arrangement is changed to change the clock signal frequency thereby to lower the error rate.

Abstract: A feed structure for an electrical component includes a slot structure with first and second longitudinal sections opposing one another and first and second interconnect segments opposing one another. The first and second interconnect segments couple the first longitudinal section with the second longitudinal section to form an opening extending through the slot structure, the opening being surrounded by the first longitudinal section, the first interconnect segment, the second longitudinal section, and the second interconnect segment. A first feed node is electrically connected to the slot structure at an intermediate region between first and second ends of the first longitudinal section, and second feed nodes are electrically coupled to the slot structure along the second longitudinal section. In a device or module, the second feed nodes are configured for electrical connection to the electrical component.

Abstract: A method of detecting faults in a register bank is disclosed. The register bank includes at least one chain of registers. The method comprises sequentially shifting parameters stored in each register of the chain to an output node of the chain and inverting each parameter and feeding each parameter back to an input node of that chain, and sequentially shifting the inverted parameters through the chain until all the non-inverted parameters have been output at the output node. A first checksum of the parameters output at the output node is calculated. The inverted parameters in each register of the chain are sequentially shifted to the output node of the chain. A second checksum of the inverted parameters output at the output node is calculated, and the first and second checksums are compared.

Abstract: Embodiments of a method and a device are disclosed. An embodiment of a method for performing physical layer operations in a communications network is disclosed. The method involves determining a value of a digital signal processor (DSP) parameter for a receiver at a first network node, at the first network node, embedding the value of the DSP parameter into a protocol data unit (PDU), and transmitting the PDU from the first network node.

Abstract: A two-step, hybrid analog-to-digital converter (ADC) includes a Delta-Sigma ADC that employs chopping to resolve MSBs, a Nyquist ADC that employs correlated double sampling (CDS) to resolve LSBs, and a combiner that combines the MSBs and the LSBs to generate a digital output signal. The Delta-Sigma ADC has first and second integrators where, after resolving the MSBs, the first integrator is re-configured to function as a reference buffer for the Nyquist ADC and the second integrator is re-configured to function as the Nyquist ADC.

Abstract: A packaged semiconductor device includes a substrate having a ground plane, a first communication port on the substrate, a second communication port on the substrate adjacent the first communication port, and grounding structures on the substrate. Each of the grounding structures is in contact with two different locations on the ground plane and is adjacent to one of the first and second communication ports. An electrically insulating material completely covers a top side of each of the grounding structures.

Abstract: One example discloses a first wireless device, including: a wireless device presence detection module configured to, generate a second wireless device presence signal if a second wireless device is within a preselected range; and generate a third wireless device presence signal if a third wireless device is within the preselected range; and a communications control module, configured to, enable communication between the first and second wireless devices in response to the second device presence signal; and disable communication between the first and third wireless devices in response to the third device presence signal.

Abstract: A system for a power switch of a multiphase power converter coupled to an inductive load including a test controller, a voltage sampling circuit, a processing circuit, and a converter. A test pulse is applied to power switches of the converter to generate a test current through the inductive load, which forward biases a body diode of a power switch during a freewheel portion after the test pulse is completed. The voltage across the body diode is sampled during the freewheel portion, and the voltage samples are converted to a voltage value and a slope value. The voltage and slope values are converted to an estimated temperature value based on a characterization of the inductive load and the body diode. The conversion may be performed by a lookup table that stores an estimated temperature value for each unique combination of the voltage and slope values.

Abstract: A communication unit (400, 500) is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one master device includes: a clock generation circuit configured to output a system clock signal; a modulator circuit (562) coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal and embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal (584); and transmit the modulated embedded master-slave clock signal (584) to the at least one slave device to synchronise the system clock signal and the frame start signal between the at least one master device (510) and at least one slave device (520).

Abstract: A circuit for controlling body biasing of a transistor is disclosed. The transistor includes a first terminal, a second terminal, a gate and a body terminal. The circuit includes a body control circuit coupled to the first terminal and the second terminal. The body control circuit is configured to connect the body terminal to ground when a voltage at the second terminal is less than a fix predefined voltage. The body control circuit is further configured to connect the body terminal to the second terminal when voltage at the first terminal is higher than voltage at the second terminal and the voltage at the second terminal is higher than the fix predefined voltage, and to connect the body terminal to the first terminal when the voltage at the first terminal is less than the voltage at the second terminal and the voltage at the first terminal is higher than the fix predefined voltage.

Abstract: A preamplifier circuit includes a first transconductor and a floating transconductor. The first transconductor receives a differential voltage from a sample-and-hold circuit and drives the floating transconductor. The first and floating transconductors output amplified versions of the differential voltage that are not affected by capacitive division, which makes the preamplifier circuit fast. The preamplifier circuit also has a low input capacitance because the floating transconductor is not connected to any external circuitry.