Abstract: A data processing system includes a graphics display component for creating an image to be displayed and a method therefor is described. The graphics display component includes: a layer selection module configured to: identify a set M of active layers for at least one pixel to be displayed; and a display controller unit, DCU, operably coupled to the layer selection module and comprising a blend manager; and at least one processor and one or more processing units. The at least one processor is configured to determine whether a number, m, of active layers in the set, M, exceeds a blend limit, n, of a maximum number of graphical surfaces that can be blended simultaneously by the DCU and, in response thereto, identify a subset N of up to n layers from the set M of active layers. The blend manager is configured to bind a first portion of active layers directly to the DCU and output any excess active layers in the set, M, that exceeds the n layers to at least one selected processing unit for blending.

Abstract: A wireless vehicle communication system (500, 600) includes a vehicle (200) having a plurality of wireless communication units (220, 240, 260) located in or attached to the vehicle (200). The plurality of wireless communication units is configured to operate in a first communication mode of operation that wirelessly transfers data to a communication unit located in a vicinity of the vehicle (200). The plurality of wireless communication units (220, 240, 260) is additionally configured to operate in a second communication mode of operation that wirelessly transfers data to at least one other of the plurality of communication units (220, 240, 260) located In or attached to the vehicle (200).

Abstract: A power amplifier cell comprising a first power amplifier, a second power amplifier and a balun. The balun comprises a first inductor and a second inductor that define a first transformer; and a third inductor and a fourth inductor that define a second transformer. The following: (i) a parasitic capacitance of the first power amplifier; (ii) a leakage inductance of the first transformer; and (iii) a capacitive coupling between the first inductor and the second inductor, contribute to a first impedance matching circuit for the first power amplifier. Also, the following (iv) a parasitic capacitance of the second power amplifier; (v) a leakage inductance of the second transformer; and (vi) a capacitive coupling between the third inductor and the fourth inductor, contribute to a second impedance matching circuit for the second power amplifier.

Abstract: A transceiver, TX/RX PHY, arranged for bi-directional data communication of a node with a counterpart node connected to a point-to-point network using differential mode signaling over a single twisted-pair cable is disclosed. The transceiver, TX/RX PHY, includes a common mode choke arranged between of the TX/RX PHY and the single twisted-pair cable and provided for common mode current suppression. Further included is a switching arrangement arranged between the TX/RX PHY, the common mode choke and the single twisted-pair cable and configured to switchably change a polarity of one of the windings of the common mode choke. A detection section is included and coupled via the switching arrangement to the common mode choke and configured to detect a common mode signal on the single twisted-pair cable in response to a transmission of a test signal by the counterpart node.

Abstract: A downlink cellular communication signal processing method includes storing resource elements from multiple resource element sequences into multiple sets of consecutive data bins of a composite signal input grid that also includes guard band bins between the sets of data bins. A frequency-domain to time-domain transformation of all values within the composite signal input grid is performed to produce a sequence of time-domain samples (e.g., a portion of an OFDM symbol). The transformation has a number of points equal to or greater than the number of bins in the multiple sets of data bins and the guard band bins. An uplink processing method includes performing a time-domain to frequency-domain transformation on a sequence of time-domain samples to produce resource elements in multiple sets of consecutive data bins of a composite signal output grid that also includes guard band bins between the sets of data bins.

Abstract: A transistor includes a substrate of a first conductivity type. An epitaxial layer of the first conductivity type is formed at a top surface of the substrate. A first region of the first conductivity type is formed as a well in the epitaxial layer. A second region of a second conductivity type is formed as a well in the epitaxial layer adjacent to the first region and the second conductivity type is opposite of the first conductivity type. A third region of the second conductivity type is formed in the first region and a portion of the first region forms a channel region between the third region and the second region. An emitter region of the first conductivity type is formed in the second region. A gate dielectric is formed over the channel region, and a gate electrode is formed on gate dielectric with the gate electrode overlapping at least a portion of second region and the third region.

Abstract: Embodiments are provided for a multi-die packaged semiconductor device including: a panel of embedded dies including a plurality of radio frequency (RF) dies, wherein each RF die includes RF front-end circuitry, each RF die has an active side that includes a plurality of pads, each RF die has a back side exposed in a back side of the panel; a plurality of antenna connectors formed on a subset of the plurality of pads of each RF die; and an array of antennas formed over a front side of the panel and connected to the plurality of antenna connectors.

Abstract: Power amplifiers such as multi-path power amplifiers, systems employing such amplifiers, and methods of implementing amplifiers and amplifier systems are disclosed herein. In one example embodiment, a multi-path power amplifier includes a first semiconductor die with an integrated first transistor having a first source-to-drain pitch, and a second semiconductor die with an integrated second transistor having a second source-to-drain pitch, where the second source-to-drain pitch is smaller than the first source-to-drain pitch by at least 30 percent. In another example embodiment, a Doherty amplifier system includes a first semiconductor die with a first physical die area to total gate periphery ratio, and a second semiconductor die with a second physical die area to total gate periphery ratio, where the second physical die area to total gate periphery ratio is smaller than the first physical die area to total gate periphery ratio by at least 30 percent.

Abstract: There is disclosed an apparatus comprising a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal (306) and a feedback clock signal (308) and to output a frequency control signal based on a phase difference between the reference clock signal (306) and the feedback clock signal (308); a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316) for generating said feedback clock signal (308) by frequency-dividing said oscillator signal; and second divider circuitry (320) for generating an output clock signal (3220 by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry (316) and said second divider circuitry (320) is adjustable to delay or advance said output clock signal (322) relative to said feedback clock signal (308). The apparatus may be a radar receiver or transceiver.

Abstract: Embodiments of a multiple-path amplifier (e.g., a Doherty amplifier) and a module housing the amplifier include a first amplifier (or first power transistor die) with a first output terminal, a second amplifier (or second power transistor die) with a second output terminal, and an impedance inverter line assembly electrically connected between the first and second output terminals. The impedance inverter line assembly includes a first transmission line and a surface mount component connected in series between the first and second output terminals. In various embodiments, the surface mount component is selected from a fixed-value capacitor, a fixed-value inductor, a tunable capacitor, a tunable inductor, and a tunable passive component network.

Abstract: Embodiments of field effect transistor (FET) circuits, RF switches, and devices include source and drain terminals coupled to an active surface of a semiconductor substrate, a channel in the substrate between the source and drain terminals, and a plurality of gate structures coupled to the active surface over the channel. A channel contact is coupled to the active surface over the channel between a pair of the gate structures. A first capacitor is electrically coupled between the channel contact and the source terminal, and a second capacitor is electrically coupled between the channel contact and the drain terminal.

Abstract: A first communication device generates a physical layer (PHY) preamble of a PHY data unit. A signal field of the PHY preamble includes i) a common block of information bits having information for multiple second communication devices and ii) a plurality of user blocks of information bits, each user block having information for a respective one of the multiple second communication devices. The common block includes a frequency resource unit allocation field that defines a plurality of frequency resource units corresponding to a PHY payload of the PHY data unit. The user blocks respectively correspond to frequency resource units defined by the frequency resource unit allocation field. Each user block includes an indication of a modulation and coding scheme (MCS) used in the corresponding frequency resource unit. Each group of two user blocks is encoded as a respective second encoded block to allow the multiple second communication devices to efficiently decode the signal field.

Abstract: A secondary side controller for a switched mode power supply, the controller comprising a first semiconductor die comprising an integrated circuit configured to provide a load connection signal; a second semiconductor die, packaged with the first semiconductor die, comprising a charge pump configured to, in response to the load connection signal received from the integrated circuit of the first semiconductor die, provide a switch signal for control of a load connection switch that controls whether or not the switched mode power supply is electrically connected to a load; wherein the presence or absence of the load connection signal is configured to control whether or not the charge pump generates the switch signal and the amplitude of the load connection signal is configured to control the voltage of the switch signal.

Abstract: An analog-to-digital converter (ADC) and a method are disclosed. The ADC has a quantizer. The quantizer comprises a linear-feedback shift register (LFSR), a decoder configured to provide a plurality of switch control signals at a plurality of decoder outputs, respectively, the plurality of switch control signals responsive to a LFSR value of the LFSR output; an electrical reference, the electrical reference having a plurality of reference outputs, the electrical reference configured to provide a plurality of reference levels at the plurality of reference outputs, respectively; a first switch providing a first switch output and a second switch output; and a comparator, the comparator having a signal input, a first reference input, and a second reference input, the first reference input connected to the first switch output, and the second reference input connected to the second switch output.

Abstract: An amplifier device includes an input terminal, an output terminal, a first transistor having a control terminal and first and second current-carrying terminals, and a class-J circuit coupled between the second current-carrying terminal of the first transistor and the output terminal and configured to harmonically terminate the first transistor. The class-J circuit may include a first resonator, characterized by a first resonant frequency substantially equal to a second harmonic frequency. The first resonator may be coupled between the second current-carrying terminal and a voltage reference. A shunt inductor that is distinct from the first resonator may be coupled between the second current-carrying terminal and the voltage reference.

Abstract: A reference voltage generator circuit (100) is disclosed, comprising a first transistor (101) having a first channel type and a second transistor (102) having a second channel type. A current source (104) is connected to a source terminal of the first transistor (101). A drain terminal of the second transistor (102) is connected to a drain terminal of the first transistor (101). The reference voltage generator circuit (100) further comprises a third transistor (103) having the second channel type, wherein a drain terminal of the third transistor (103) is connected to a source terminal of the second transistor (102). A node between the source terminal of the second transistor (102) and the drain terminal of the third transistor (103) is connected to a gate terminal of the first transistor (101). A connection for a reference voltage (Vrc) is provided between the current source (104) and the source terminal of the first transistor (101).

Abstract: Internally-shielded microelectronic packages having increased resistances to electromagnetic cross-coupling are disclosed, as are methods for fabricating such microelectronic packages. In embodiments, the internally-shielded microelectronic package includes a substrate having a frontside and a longitudinal axis. A first microelectronic device is mounted to the frontside of the substrate, while a second microelectronic device is further mounted to the frontside of the substrate and spaced from the first microelectronic device along the longitudinal axis. An internal shield structure includes or consists of a shield wall, which is positioned between the first and second microelectronic devices as taken along the longitudinal axis. The internal shield structure is at least partially composed of a magnetically-permeable material, which decreases electromagnetic cross-coupling between the first and second microelectronic devices during operation of the internally-shielded microelectronic package.

Abstract: Embodiments of a method and a device are disclosed. A method for performing operations in a communications network is disclosed. The method involves, determining, at a first network node in a communications network, that a DSP of a receiver of a network node in the communications network can operate at a reduced functionality level, and communicating the determination from the first network node to a second network node in the communications network in a protocol data unit (PDU), wherein the DSP of a receiver of a network node that can operate at a reduced functionality level is a DSP of a receiver of one of the first network node and the second network node.

Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a method for performing physical layer operations in a communications network is disclosed. The method involves determining a desired error management mode for a receiver at a first network node, at the first network node, embedding an indication of the desired error management mode into a forward error correction (FEC) frame, and transmitting the FEC frame from the first network node. In an embodiment, embedding an indication of the desired error management mode into an FEC frame includes embedding an operations, administration, and management (OAM) word into the FEC frame to communicate the indication of the desired error management mode.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a network interface device is disclosed. The device includes a network interface configured to provide an interface to a network, a functional component interface configured to provide an interface to a functional component, and distributed test logic located in a path between the network interface and the functional component interface and configured to manage test information related to testing of the functional component and to communicate test information between the network interface and the distributed test logic and between the functional component interface and the distributed test logic.