Abstract: Embodiments of a device and method are disclosed. In an embodiment, a network interface device is disclosed. The device includes a network interface configured to provide an interface to a network, a functional component interface configured to provide an interface to a functional component, and distributed test logic located in a path between the network interface and the functional component interface and configured to manage test information related to testing of the functional component and to communicate test information between the network interface and the distributed test logic and between the functional component interface and the distributed test logic.

Abstract: Embodiments of a method and a device are disclosed. An embodiment of a method for performing physical layer operations in a communications network is disclosed. The method involves determining a value of a digital signal processor (DSP) parameter for a receiver at a first network node, at the first network node, embedding the value of the DSP parameter into a protocol data unit (PDU), and transmitting the PDU from the first network node.

Abstract: A method is provided for authenticating a log message in a distributed network having a plurality of nodes coupled to a serial bus. In the method, a log session is started by a first device at a first node of the plurality of nodes. A first counter value is provided by the first device to the serial bus. A log message is generated by a second device at a second node of the plurality of nodes. A second counter value is generated by the second device. A log message payload is generated for the log message, wherein the log message payload includes a log message authentication code. A computation of the log message authentication code includes the first counter value and the second counter value. The second device does not store the first counter value in a non-volatile memory on the second device.

Abstract: A method including receiving, by a radio equipment control (REC) device of a wireless communication system over an interface link, time domain compressed data from a radio equipment (RE) device at a first data transmission rate. The method further including transforming, by the REC device, the time domain compressed data to frequency domain decompressed full rate data for a second transmission data rate utilizing a Fast Fourier processing engine of the REC device.

Abstract: A semiconductor device comprising a pn junction diode and a method of making the same. The device includes a semiconductor substrate having a first conductivity type. The device also includes a buried oxide layer located in the substrate. The device further includes a semiconductor region having a second conductivity type extending beneath the buried oxide layer to form a pn junction with a semiconductor region having the first conductivity type. The pn junction is located beneath the buried oxide layer and extends substantially orthogonally with respect to a major surface of the substrate. The device also includes a field plate electrode comprising a semiconductor region located above the buried oxide layer for modifying an electric field at the pn junction by application of a potential to the field plate electrode.

Abstract: Current controlled multiplying digital-to-analog converters (MDACs) and related methods are disclosed for time-interleaved analog-to-digital converters (ADCs). For one embodiment, a circuit includes an MDAC having an amplifier that converts a voltage to an output current, a variable load that is dependent upon a digital value and that controls the output current from the amplifier, and an array of comparators that receive the voltage and output the digital value to the variable load. The digital value represents at least a portion of a digital conversion of the voltage. Further, the circuit can include a phased current generator that receives the output current and generates time-interleaved currents where each time-interleaved current is a sampled copy of the output current.

Abstract: According to a first aspect of the present disclosure, a fingerprint processing system is provided, which comprises: a set of sensor plates; a measurement unit configured to measure one or more capacitances on the sensor plates; a processing unit configured to process the measured capacitances; wherein the measurement unit is configured to concurrently measure capacitances on subsets of the set of sensor plates; wherein the processing unit is configured to process the concurrently measured capacitances. According to a second aspect of the present disclosure, a corresponding method of processing a fingerprint in a fingerprint processing system is conceived. According to a third aspect of the present disclosure, a corresponding computer program is provided.

Abstract: Wireless receivers and related methods with interferer immunity are disclosed. The receiver includes a receive (RX) front-end, a power level detector, and an automatic gain controller (AGC). The RX front-end includes circuit(s) having variable gains, and the power level detector outputs a power level indicator. The AGC receives the power level indicator and outputs the gain settings to the variable-gain circuits within the RX front-end. Further, the AGC is configured to adjust the gain settings within a first gain range when not receiving data frames and to adjust them within a second gain range when receiving data frames. The second gain range is a restricted version of the first gain range. Further, the AGC can be configured to detect and store gain settings within a sliding time window when data frames are not being received and to use these stored gain settings to determine the second gain range.

Abstract: A structure for improved noise signal isolation in semiconductor devices. In one embodiment, the structure includes a second-conductivity type substrate, a 1st first-conductivity type well, a 1st first-conductivity type layer, a second-conductivity type layer positioned between the 1st first-conductivity type well and the 1st first-conductivity type layer. The structure also includes a 2nd first-conductivity type well, and a 2nd first-conductivity type layer positioned between the 2nd first-conductivity type well and the 1st first-conductivity type layer. The 1st first-conductivity type layer and the second-conductivity type layer are positioned between the P type substrate and the 1st first-conductivity type well, and the 1st first-conductivity type well is laterally separated from the 2nd first-conductivity type well.

Abstract: Foreign object detection (FOD) is provided for wireless energy transfer systems. A transmitter receives an input voltage, converts it to an output current, supplies the output current to a transmit coil, and samples a first set of analog signals to generate a first set of digital values. A receiver converts a current induced in a receive coil by energy transferred from the transmit coil into an output voltage, samples a second set of analog signals to generate a second set of digital values, and communicates the second set of digital values to the transmitter. The transmitter generates a FOD signal based upon the first and second sets of digital values that indicates detection or non-detection of a foreign object within the energy transfer. In further embodiments, a comparison of the detected power loss or efficiency to expected power loss or efficiency is used to generate the FOD signal.

Abstract: A Time to Digital converter (TDC) may have a Vernier architecture of multiple successive modules arranged in series. Each of the modules may output an indication of a differential in phase between two received signals. Each module may include two signal lines for the received signals, and it may be desirable to calibrate the two signal lines. To this end, a signal output from a proceeding module may be provided to both signal lines of a succeeding module and used as a reference or calibration signal to calibrate the two signal lines of the module.

Abstract: Devices, systems and methods are provided for calibrating a transducer. One exemplary method involves determining a transfer function for the transducer based on a measured response of the transducer to an applied electrical signal, determining a set of values for a plurality of response parameters associated with the transducer based on the transfer function, determining a calibration coefficient value associated with the transducer based at least in part on the set of values and a correlation between physical sensitivity and the plurality of response parameters, and storing the calibration coefficient value in association with the transducer.

Abstract: According to a first aspect of the present disclosure, a fingerprint sensing system is provided, the system comprising: a plurality of sensors and a controller, wherein the controller is configured to selectively activate at least one of the plurality of sensors; wherein the controller is further configured to develop and measure at least one first capacitance, the first capacitance developing in response to a capacitance between a surface of an active sensor and a surface of a finger; and wherein the controller is further configured to develop at least one second capacitance, the second capacitance developing in response to a capacitance between a surface of an inactive sensor and the surface of the finger. According to a second aspect of the present disclosure, a corresponding fingerprint sensing method is conceived.

Abstract: Embodiments of a clock synchronization unit of an All Digital Phase-Locked Loop (ADPLL), a successive approximation register (SAR) Time-to-Digital Converter (TDC) of an ADPLL and a method for clock synchronization in an ADPLL are disclosed. In one embodiment, a clock synchronization unit of an ADPLL includes a two-flop synchronizer, a phase frequency detector (PFD) connected to the two-flop synchronizer, and a synchronization control circuit configured to control the two-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal and to control the two-flop synchronizer and the PFD to replace a performance of the clock synchronization between the reference clock input signal and the divided clock input signal with a PFD operation. Other embodiments are also described.

Abstract: A mechanism for secure enrollment of devices with a cloud platform is provided. This serves as a foundation for securing devices, such as edge computing and internet-of-things gateways, that can be provisioned and managed from the cloud. A public key infrastructure mechanism is provided for enrollment that is split into three phases. The first and second phases of the secure enrollment process authenticate the device and ensure that the device is within agreed to manufacturing limits for the device manufacturer. The third phase of the secure enrollment process provides a long-term operating certification to the device for cloud resource access.

Abstract: A communications device includes aspects for improving reception of transmissions with first-adjacent co-channel interference signals corresponding to digitally-modulated side-bands of in-band on-channel (IBOC) broadcasted signals. The communications device may include a radio frequency (RF) signal-reception circuit including two RF-signal paths driven in response to signals received via at least two respective antennas, and configured to respond to signals carried in the respective RF-signal paths by providing pre-processed RF output signals. The communications device may further include a beam-forming circuit driven in response to signals received at the at least two respective antennas and configured and arranged to facilitate first-adjacent interference cancellation (FAC).

Abstract: A first communication device receives an aggregate medium access control data unit (MAC) protocol data unit (A-MPDU) that aggregates multiple MAC protocol data units from a second communication device. The first communication device generates an acknowledgment data unit that includes a length indication that indicates a length of an acknowledgement field and the acknowledgment field of the indicated length. The length of the acknowledgement field is selected from a subset of predetermined lengths, among a set predetermined lengths, that includes multiple predetermined lengths that do not exceed a maximum number of MAC protocol data units that can be included in the A-MPDU. The maximum number of MAC protocol data units is limited by a buffer size negotiated in an acknowledgement setup procedure previously conducted between the first communication device and the second communication device. The first communication device transmits the acknowledgment data unit to the second communication device.

Abstract: Digital calibration systems and related methods are disclosed for multi-stage analog-to-digital converters (ADCs). For one embodiment, a multi-stage ADC includes an initial ADC, an additional ADC, and calibration logic. The initial ADC generates an output signal and N-bit digital values that are based upon an input signal. The additional ADC receives the output signal from the initial ADC and generates M-bit digital values that are based upon the output signal. The calibration logic receives the N-bit digital values and the M-bit digital values and generates correction values. The correction values are based upon differences between maximum values and minimum values for M-bit digital values associated with different regions determined by the N-bit digital values. Digital conversion outputs for the multi-stage ADC are provided as combinations of the N-bit digital values and the M-bit digital values corrected with the correction values.

Abstract: Embodiments of a magnetoresistive random access memory (MRAM) diagnostic system are provided, which includes: preconditioning all bit cells in an MRAM cell array to a data value of one during a diagnostic mode, wherein the MRAM cell array is implemented in an active side of a semiconductor substrate; applying a first magnetic disturb field having a predetermined field strength to the MRAM cell array, subsequent to the preconditioning, wherein the first magnetic disturb field is generated by an antenna implemented in a number of layers of conductive and dielectric material over the active side of the semiconductor substrate; performing a first error correcting code (ECC) read operation to read the MRAM cell array, subsequent to the applying the first magnetic disturb field; and in response to detecting at least one uncorrectable read during the first ECC read operation, setting a fail state and exiting the diagnostic mode.

Abstract: Embodiments described herein provide a method for dynamically scaling log-likelihood ratio (LLR) values of received data bits before decoding the received data bits. A plurality of data bits are received corresponding to a data packet. A first set of data bits of a first type are determined from the plurality of data bits based on a modulation scheme corresponding to the received data bits. A first LLR histogram is generated corresponding to the first set of data bits of the first type. A first scaling factor is calculated based on the first LLR histogram such that a first LLR value range corresponding to the first set of data bits is expanded to a maximum LLR value range. All LLR values are scaled by the first scaling factor. The scaled LLR values corresponding to the plurality of data bits are sent to a decoder.