Abstract: An embedded system is described. The embedded system includes a processing circuit comprising ‘Q’ processing units that can be operated in parallel. A memory is operably coupled to the processing circuit and includes at least input data. The processing circuit is configured to support an implementation of a non-power-of-2 fast Fourier transform of length N using a multiplication of at least two smaller FFTs of a respective first length N1 and second length N2, where N1 and N2 are whole numbers. The processing circuit is further configured to employ a customized instruction configured to perform an FFT operation of length less than ‘Q’ using a first of the at least two smaller FFTs.

Abstract: Embodiments in accordance with present disclosure are directed to methods, devices, and apparatuses. An example embodiments include an apparatus comprising a differential data bus and a transceiver circuit. The transceiver circuit includes a differential driver and differential receiver that operate and communicate in the first communication mode and the second communication mode. The transceiver circuit is configured to switch to the second communication mode in response detecting a signal edge of a signal input received at the differential driver by at least one of: the differential driver being configured and arranged to drive a differential driver voltage on the differential data bus to a voltage that overrides a predefined voltage; and pre-conditioning the differential receiver for the transition to the second communication mode.

Abstract: Receivers and methods of testing are described. A receiver includes a plurality of receiver channels, each including an amplifier for receiving a signal from an antenna and a mixer downstream of the amplifier. A test signal generating circuit is configured to generate test signals. A signal path connects the test signal generating circuit and each receiver channel and couples to each receiver channel at a coupling between the amplifier and a mixer. A test signal from the test signal generating circuit is injectable to the parts of the receiver channel downstream of the amplifier. The test signal may alternatively be injected into the entire receiver channel. The receivers and methods may be used in wireless systems, such as radar systems and radio systems.

Abstract: One example discloses a near-field electromagnetic induction (NFEMI) antenna device, having: a coil, having first and second coupling points, configured to generate and/or receive a magnetic (H-field) near-field signal; a conductive structure having first and second coupling points separated by a distance; first and second feed points configured to carry a current from a transmitter and/or to a receiver circuit; wherein the first coupling point of the conductive structure is coupled to the first feed point and wherein the second coupling point of the conductive structure is coupled to the first coupling point of the coil; wherein the second coupling point of the coil is coupled to the second feed point; and wherein the conductive structure is configured to generate an electric (E-field) near-field in response to the current flowing over the distance between the first and second coupling points of the conductive structure.

Abstract: An integrated circuit includes a voltage monitor circuit having a first input coupled to a reference voltage and a second input, a successive approximation register (SAR) circuit having an input coupled to an output of the voltage monitor circuit, a low drop out (LDO) regulator having an input coupled to an output of the SAR circuit and an output coupled to the second input, a discharge circuit coupled to the LDO output, voltage sensing circuit having a first input coupled to the reference voltage during a trim mode and coupled to the LDO output during a monitor mode, having a second input coupled to the reference voltage, and an output which asserts a sense indicator that indicates when a voltage at the first input goes higher or lower than the reference voltage by a predetermined amount. Control circuitry is configured to, during trim mode, periodically discharge the LDO output voltage.

Abstract: An apparatus comprising: a substrate; an integrated circuit region formed in the substrate; a seal ring disposed in the substrate to form a ring around the integrated circuit region, the seal ring configured to provide for protection against one or more of moisture ingress and ion ingress to the integrated circuit region and crack propagation through the substrate; and a defect sensor comprising a conductive track formed of at least one conductive layer in the substrate, the conductive track disposed outwardly of the seal ring and arranged to at least partially surround the integrated circuit region and seal ring, the conductive track having a first end terminal and a second end terminal to receive a detection signal therebetween to pass through the conductive track to detect a break in the conductive track and thereby a defect in the substrate.

Abstract: A continuous buried doped isolation region in a substrate of a die. The substrate includes an isolation ring structure surrounding a first area of the die. The continuous buried doped isolation region is of a net first conductivity type and is located in the first area. The continuous buried doped isolation region including a first portion having a net first conductivity type dopant concentration of at least a first level located in an interior region of the first area and extending to a sidewall of the isolation ring structure. The first portion does not extend to the sidewall of the isolation ring structure in a location of a corner area of the first area. The corner area is defined by the isolation ring structure. A second portion of the continuous buried doped isolation region in the corner area has a net first conductivity type dopant concentration of a second level that is lower than the first level.

Abstract: A method for wafer dicing and removing separated integrated circuit (IC) dies from a carrier substrate includes mounting a wafer on a substrate using an adhesive layer, laser scribing the adhesive layer to create defect regions in the adhesive layer, and performing a breaking step to separate the laser-scribed adhesive layer into separated adhesive portions corresponding to the IC dies. For a stealth-dicing (SD) technique, defect regions also are created in the wafer using a laser and the breaking step is an expansion step that simultaneously separates the dies and corresponding portions of adhesive. For a dice-before-grind (DBG) technique, the dies are separated by backside grinding before the breaking step. Efficient adhesive-layer separation is achieved with reduced backside chipping associated with conventional blade dicing.

Abstract: Embodiments of an amplifiers and integrated circuits include a first transistor and a second transistor. A second current-carrying terminal of the first transistor may be coupled to a first current-carrying terminal of the second transistor and the control terminal of the second transistor may be coupled to a low impedance alternating current (AC) potential node. A bias network that includes a first circuit element and a second circuit element couples the second current-carrying terminal of the second transistor to the control terminal of the second transistor. The first circuit element may be configured to apply a portion of a potential at the second current-carrying terminal of the second transistor to the control terminal of the second transistor, and the second circuit element may be coupled between the control terminal of the second transistor and a fixed potential.

Abstract: A method includes: calculating a first calibration temperature based on a first ratio of a known external voltage to a delta voltage that is a difference between first and second base-emitter voltages of first and second sensing transistors, calculating a first sensed temperature based on a second ratio of the first base-emitter voltage to the delta voltage, adjusting one or more temperature fitting parameters based on a comparison of the first sensed temperature with the first calibration temperature; activating the on-chip heater; calculating a second calibration temperature based, at least in part, on a third ratio of the known external voltage to the delta voltage, calculating a second sensed temperature based on a fourth ratio of the first base-emitter voltage to the delta voltage, adjusting at least one of the one or more temperature fitting parameters based on a comparison of the second sensed temperature with the second calibration temperature.

Abstract: A secure communication between computer systems over a network, such as the Internet, is performed utilizing an enhancement to the IKEv2 key exchange protocol that provides more security by exchanging the IKE_SA_INIT messages in a secure and protected manner. Cryptographic suites are utilized to encrypt and authenticate the IKE_SA_INIT exchange messages in order to prevent cyberattacks against such a messaging protocol.

Abstract: Most of the AC-DC converters have an analog control loop, which costs additional pins for the compensator, and there are limited options to change settings when, for example, the output voltage needs to change. This specification discloses systems and methods, where a delta-sigma ADC (analog-to-digital converter) is used to digitize the input voltage. The filter after the delta-sigma ADC can give a big delay, which reduces the phase margin of the control loop. To minimize the delay, this invention ensures that, when the setpoint is reached, the input of the delta-sigma modulator is in the middle of the input range. In some embodiments, a digital control loop can be implemented using a delta-sigma modulator together with a PI controller (proportional-integrator controller).

Abstract: A wireless repeater system includes an antenna configured to receive a magnetic wake-up signal, a near field communication (NFC) receiver configured to receive a wake-up pattern and compare the received wake-up pattern with a stored wake-up pattern, and an NFC transmitter configured to transmit an output magnetic signal using the stored wake-up pattern to an external device, wherein the transmission of the output magnetic signal is synchronized with the received wake-up pattern to form a superimposed magnetic signal.

Abstract: A first-transceiver system for use in an antenna diversity scheme. The first-transceiver system comprising: a first-receiver; a first-time/clock-generation-unit; a first-transmitter; and a timing-controller. The first-receiver is configured to receive a wireless first-common-signal from a third-party-transmitter, wherein the first-common-signal is representative of a common-signal transmitted by the third-party-transmitter. The timing-controller is configured to: receive signaling representative of the first-common-signal; receive signaling representative of a wireless second-common-signal as received at a second-transceiver, the wireless second-common-signal being representative of the common-signal; and generate a timing-signal based on the first-common-signal and the second-common-signal.

Abstract: Power amplifiers, amplifier systems, and related methods are disclosed herein. In one example embodiment, the amplifier system includes a bias controller that automatically sets a bias voltage of a power amplifier device by monitoring a reference device that is in a scaled relationship with the power amplifier device, and integrally is formed with the power amplifier device on a same semiconductor die. The bias controller can compare a voltage at an input to the reference device to a reference voltage, and then adjust a voltage at a control input of the reference device to a stabilized voltage that induces the reference device to drive the voltage at the input to the reference device equal to the reference voltage. Finally, the bias controller can transform, based on the scaled relationship, the stabilized voltage into a bias voltage applied to a control input of the power amplifier device.

Abstract: An integrated circuit comprising: an input terminal configured to receive a failure-event-signal representative of a failure event; a first output terminal configured to provide a first-failure-signal; and a second output terminal configured to provide a second-failure-signal; and a processing block configured to: set the first-failure-signal based on the failure-event-signal; and set the second-failure-signal, at a predetermined time interval after the first-failure-signal is set. The processing block further comprises a switch configured selectively, based on a received digital-error-signal to either: set the second-failure-signal based on a digital-counter-output-signal; or set the second-failure-signal based on an analogue-trigger-signal.

Abstract: A method of computing a message authentication code (MAC) for a message having a common part and an independent part using a constrained processor, including: performing a MAC function on the common part of the message using a first secret key to produce a first output; performing a pseudorandom function on the independent part of the message using a second key to produce a second output, wherein the computation time of the pseudorandom function is significantly less than the computation time of the MAC function; and combining the first output and the second output to produce a computed MAC for the message.

Abstract: There is provided a method of operating a security token, said security token comprising a secure element and a microcontroller unit being coupled to said secure element, wherein: the secure element receives an authentication command from a host device while the microcontroller unit is in a first sleep state; the secure element decodes the authentication command, sends a corresponding authentication request to the microcontroller unit and subsequently enters into a second sleep state; the microcontroller unit wakes up upon receiving the authentication request and subsequently determines an amount of available power; the microcontroller unit processes the authentication request only if the amount of available power exceeds a threshold. Furthermore, a corresponding computer program product and a corresponding security token are provided.

Abstract: A millimeter-wave wireless multiple antenna system (80) and method (100) are provided in which a UE (120) uses a multi-antenna subsystem (81) to identify a plurality of m strongest transmit beams (122) from the base station (110) based on power measurements of a plurality of synchronization signal blocks (SSBs) transmitted on a corresponding plurality of transmit beams by the base station (110), and to generate multiple uplink random access channel (RACH) preambles (123) that is sent (124) to the base station (110) to identify the plurality of m strongest transmit beams and relative weights for each of the plurality of m strongest transmit beams which are used by the base station (112) to generate an optimal downlink transmit beam for use in sending a RACH response to the UE (120).

Abstract: A millimeter-wave wireless multiple antenna system (80) and method (100) are provided in which a UE (120) uses a multi-antenna subsystem (81) to identify a plurality of m strongest transmit beams (122) from the base station (110) based on power measurements of a plurality of synchronization signal blocks (SSBs) transmitted on a corresponding plurality of transmit beams by the base station (110), and to generate a composite uplink random access channel (RACH) preamble (123) that is sent (124) to the base station (110) to identify the plurality of m strongest transmit beams and relative weights for each of the plurality of m strongest transmit beams which are used by the base station (112) to generate an optimal downlink transmit beam for use in sending a RACH response to the UE (120).