Abstract: Pre-fetching instructions for tasks of an operating system (OS) is provided by calling a task scheduler that determines a load start time for a set of instructions for a particular task corresponding to a task switch condition. The OS calls, and in response to the load start time, a loader entity module that generates a pre-fetch request that loads the set of instructions for the particular task from a non-volatile memory circuit into a random access memory circuit. The OS calls the task scheduler to switch to the particular task.

Abstract: A voltage regulator has an output driver current mirror circuit and one or more control circuits. The output driver current mirror circuit includes an output driver transistor, a tunable resistance circuit, and a diode-connected transistor. The output driver transistor has one current electrode coupled to a supply voltage and another current electrode coupled to an output terminal for providing the output voltage of the voltage regulator. The tunable resistance circuit has one terminal coupled to a control electrode of the output driver transistor, and another terminal coupled to a current electrode of the diode-connected transistor. The one or more control circuits includes a comparator for controlling a current provided to the output driver current mirror in response to a feedback signal from the output terminal.

Abstract: An embedded computer system includes a processor, an interrupt source, an interrupt controller and a cache memory subsystem. In response to a request from the processor to read a data element, the cache memory subsystem fills cache lines in a cache memory with data elements read from an upper-level memory. While filling a cache line the cache memory subsystem is unable to respond to a second request from the processor which also requires a cache line fill. In response to receiving an indication from an interrupt source, the interrupt controller provides an indication substantially simultaneously to the processor and to the cache memory subsystem. In response to receiving the indication from the interrupt controller, the cache memory subsystem terminates a cache line fill and prepares to receive another request from the processor.

Abstract: A method performed by a radio base station, the method including receiving streaming data information, the data information includes a first portion from a first set of antenna carriers and a second portion from a second set of antenna carriers, wherein the first portion is to be processed prior to the second portion. The method further including streaming the first portion of the data information from a radio equipment control device in a first data frame over an interface link that is configured to operate based on a first mapping configuration that indicates a set of locations of the first data frame at which the first portion of information is to be streamed, and streaming the second portion of the data information from the REC device in a second data frame over the interface link that is configured to operate based on a second mapping configuration.

Abstract: An apparatus for reporting traffic information comprises a mobile device. The mobile device comprises one or more sensor for monitoring an environmental condition, a memory for storing one or more template. A signal processing module is present for comparing the monitored environmental condition with a selected one of the one or more template indicative of a type of environmental condition. The module generates a event notification message when the monitored environmental condition matches the selected template, the event notification message including information of the type of environmental condition. A transmitter is arranged to transmit the event notification message to a remote station.

Abstract: The embodiments described herein provide a radar device and method that can provide improved sensitivity. In general, the embodiments described herein provide a saturation detector and reset mechanism coupled to a radar receiver. The saturation detector is configured to detect saturation events in the radar receiver, and the reset mechanism is configured to reset at least one filter unit in the radar receiver in response to detected saturation events. As such, the embodiments can facilitate improved radar sensitivity by reducing the effects of saturation events in the radar receiver.

Abstract: A task control circuit maintains, in response to task event information, a task information queue that includes task information for a plurality of tasks. Based upon the task information in the task information queue, a future task switch condition is identified as corresponding to a task switch time for a particular task of the plurality of tasks. A load start time is determined for a set of instructions for the particular task. A pre-fetch request is generated to load the set of instructions for the particular task into the memory circuit. The pre-fetch request is forwarded to a hardware loader circuit. In response to the task switch time, a task event trigger is generated for the particular task. The hardware loader circuit is used to load, in response to the pre-fetch request, the set of instructions from a non-volatile memory into the memory circuit.

Abstract: An integrated circuit device includes a peripheral control circuit configured to receive a low power intent signal from a first processor, and a first control register in the peripheral control circuit. The first control register includes a peripheral enable indicator for each processor that can use a first peripheral. Acknowledgement logic circuitry is configured to assert a first low power acknowledgement signal when the first processor issuing the low power intent signal has enabled use of the first peripheral as indicated by the peripheral enable indicator for the first processor in the first control register.

Abstract: An integrated circuit device is formed to include a plurality of vias that connect an antenna to a ground reference. This configuration of the integrated circuit device provides an electrical path from the antenna to ground, thereby preventing the buildup of charge at the antenna. The vias thereby reduce the likelihood of a potential difference between components of the integrated circuit device and the antenna, in turn reducing the likelihood of electrostatic discharge at the integrated circuit device.

Abstract: Apparatus for testing a device by delivering an electrostatic discharge signal to one or more device terminals, comprising a first part configured for mechanically mounting the device and comprising one or more first part connectors for electrically coupling to the one or more device terminals and thus providing electrical access to the one or more device terminals, a second part comprising one or more second part connectors configured for electrically coupling the one or more first part connectors to the one or more second part connectors for testing the device via the second part connectors, and a guide arranged for mechanically moving the first part relative to the second part. The guide is configured to physically disconnect the one or more first part connectors from the one or more second part connectors while the electrostatic discharge signal is delivered to the one or more device terminals.

Abstract: A method for transmitting a measured value in a data transmission signal, the method including: introduction of the measured value into the data transmission signal; introduction of error information after said measured value into the data transmission signal, from which information it can be deduced whether the measured value contains an error; and introduction of evaluation information which describes the error information into the data transmission signal after the error information, if the measured value contains an error.

Abstract: A method of operating a cache-coherent computing system includes storing first state information corresponding to a first reservation for a first exclusive access to a first memory address requested by a first thread executing on a first processor of a first plurality of processors. The method includes transmitting an output atomic response transaction indicating a status of the first reservation to a coherency interconnection in response to issuance of the first exclusive access to the coherency interconnection. The output atomic response transaction is based on first state information.

Abstract: A compensation circuit for compensating for an input charge at a first input of a sample and hold circuit, comprising: a first buffer, a first compensation capacitor comprising a first compensation terminal switchable between a first buffer input and a first buffer output, and a second compensation terminal switchable between the first buffer output and a reference terminal, and a control circuit to switch the first compensation terminal to the first buffer1 output and the second compensation terminal to the reference terminal during sampling, for storing a compensation charge into the first compensation capacitor, and to switch the first compensation terminal to the first buffer input and the second compensation terminal to the first buffer output during holding, for discharging the first compensation capacitor into the first input. The compensation charge is substantially equal to the input charge.

Abstract: A nonlinear MIMO-OFDM detector includes a vector arithmetic unit (VAU) that sequentially computes first metrics corresponding to a first current tree level of a first search tree and second metrics corresponding to a second current tree level of a second search tree. A sorting and indexing unit (SIU) that sorts the first metrics and the second metrics sequentially received from the VAU and that sequentially provides first indices of lowest first metrics and second indices of lowest second metrics to the vector arithmetic unit. The lowest first metrics are first inputs to the VAU for a first next tree level of the first search tree and the lowest second metrics are second inputs to the VAU for a second next tree level of the second search tree. The VAU and the SIU are pipelined to compute the second metrics concurrently with sorting and indexing of the first metrics.

Abstract: An outphasing amplifier having: a first branch arranged to receive and process a first branch signal, the first branch signal being phase modulated, with constant amplitude envelope; and a second branch arranged to receive and process a second branch signal, the second branch signal being phase modulated, with constant amplitude envelope, and at least a portion of the second branch signal anti-phase from the first branch signal, wherein each branch includes: circuitry arranged to process the signal to reduce the energy in sidebands of the signal away from the central frequency, while retaining the phase information in the signal; and an amplifier arranged to amplify the filtered and re-asserted branch signal.

Abstract: An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate. The integrated circuit also includes a metallization stack located on a major surface of the semiconductor substrate. The metallization stack includes a plurality of metal layers including patterned metal features. Each metal layer of the metallization stack is separated by an intervening dielectric layer. The metallization stack forms a first grid including patterned metal features for supplying power and signal connections to components of the integrated circuit located in the semiconductor substrate. The metallization stack also forms a second grid for securing the integrated circuit against electromagnetic attacks. The second grid includes patterned metal features interspersed with the patterned metal features of the first grid in at least some of the metal layers of the metallization stack. The patterned metal features of the second grid are electrically connected to the first grid.

Abstract: A power converter including: a dual output resonant converter including a first output, a second output, a common mode control input, and a differential mode control input, wherein a voltage/current at the first output and a voltage/current at the second output are controlled in response to a common mode control signal received at the common mode control input and a differential mode control signal received at the differential mode control input; and a dual output controller including a first error signal input, a second error signal input, a delta power signal input, a common mode control output, and a differential mode control output, wherein the dual output controller is configured to generate the common mode control signal and the differential mode control signal in response to a first error signal received at the first error signal input and a second error signal received at the second error signal input, wherein the first error signal is a function of the voltage/current at the first output and the seco

Abstract: A switched current control module comprises a hysteretic control component arranged to receive high and low threshold values and an indication of a current flow through a load, and to output a switched current control signal based on a comparison of the current flow indication to the high and low threshold values. A threshold generator is arranged to generate the high and low threshold values based on a base threshold value and a hysteretic excursion value. A base threshold value generator is arranged to generate the base threshold value based on the current flow indication and a setpoint value. A hysteretic excursion value generator is arranged to receive an indication of a switching frequency of the switched current control signal output by the hysteretic control component, and to generate the hysteretic excursion value based on the indicated switching frequency of the switched current control signal.

Abstract: The disclosure relates to a method of operating a system, the system comprising a near field communication, NFC, tag, an NFC device associated with a user of the system and a computer, the method comprising: the NFC device requesting a message from the NFC tag; the NFC tag generating a message comprising a representation of a counter value; the NFC tag sending the message to the NFC device; the NFC device generating a request comprising the representation of the counter value in response to receiving the message; the NFC device sending the request to a computer; the NFC device submitting user authentication data to the computer; and the computer executing an operation on verification of the counter value and the authentication data.

Abstract: One example discloses a health monitoring device, including: a communications circuit configured to receive a set of health sensor data based on a body surface; and a near-field antenna, coupled to the circuit, and conformally coupled to the body surface.