Abstract: A semiconductor device includes a lead frame site including a die attach region and corrugated metal leads around the die attach region. Each of the corrugated metal leads includes two or more corrugations. Each of the two or more corrugations includes a first flat horizontal portion, a first vertical portion with a first end directly adjacent and connected to a first end of the first flat horizontal portion, a second flat horizontal portion with a first end directly adjacent and connected to a second end of the first vertical portion, and a second vertical portion with a first end directly adjacent and connected to a second end of the second flat horizontal portion. The first flat horizontal portion is in a different plane than the second flat horizontal portion.

Abstract: Various configurations and arrangements of various communication devices are disclosed. Various integrated circuits that form these communication devices can be fabricated onto one or more semiconductor substrates, chips, and/or dies using a high voltage semiconductor process, a low voltage semiconductor process, or any combination thereof. Some of these high voltage and/or low voltage semiconductor process integrated circuits can be fabricated along with other high voltage and/or low voltage semiconductor process integrated circuits of other modules onto a single semiconductor substrate, chip, and/or die. This allows the low voltage semiconductor process integrated circuits and/or high voltage semiconductor process integrated circuits of one module to be combined with low voltage semiconductor process integrated circuits and/or high voltage semiconductor process integrated circuits of another module of the communication device.

Abstract: In order to reduce latency of elliptical curve digital signature generation a portion of the digital signature is pre-calculated before receipt of the message hash using an unmodified ECDSA computing engine. After the message hash is received, the digital signature is completed without using the ECDSA computing engine. Applications include generating digital signatures for the safety messages in Intelligent Transport Systems.

Abstract: A method for stress testing a device under test (DUT) having a plurality of pins includes generating a stress test pattern which independently stresses each pin of the plurality of pins, wherein the stress test pattern includes a plurality of test vector, and applying each test vector to the plurality of pins for a predetermined amount of time. The method further includes, after applying all the test vectors of the stress test pattern, applying a programmable load to each pin independently and after applying each programmable load, comparing an output voltage of each pin to a predetermined voltage range to form an output vector for each pin.

Abstract: A semiconductor component is formed by providing a substrate having partially formed first and second transistors, a base electrode stack formed over the transistors, first and second emitter windows formed in the electrode stack over first and second collector regions of the transistors, and an oxide layer extending over the collector regions. A process entails forming a mask layer in a selected emitter window, optionally forming a selectively implanted collector (SIC) in an un-masked emitter window, and removing an oxide layer and forming an epitaxial layer in the un-masked emitter window. The process further entails forming an oxide layer over the epitaxial layer and repeating the operations of forming a mask layer for another selected emitter window, optionally forming a SIC in another un-masked emitter window, and removing an oxide layer and forming an epitaxial layer in the un-masked emitter window. The epitaxial layers may have different epitaxial growth profiles.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes a bipolar transistor device connected between a first node and a second node, a series protection device connected in series with the bipolar transistor device, and a diode device connected between the second node and a third node. A drain terminal of an NMOS device to be protected is connectable to the first node. A body of the NMOS device to be protected is connectable to the second node. A source terminal of the NMOS device to be protected is connectable to the third node. The diode device and the bipolar transistor device are configured to form a parasitic silicon controlled rectifier. Other embodiments are also described.

Abstract: A MEMS sensor for measuring rotational motion about a first axis includes a frame, a base structure under the frame, a drive mass mounted in the frame for rotational movement about a second axis perpendicular to the first axis, and a first drive paddle in the drive mass. A first link includes a first end coupled to a first spring that movably couples the first drive paddle to the drive mass and a second end coupled to a second spring that movably couples the first link to the frame. A drive system includes an electrode aligned to exert electromotive force to pivot the first drive paddle and move the drive mass about the second axis. Deflection of the drive mass is greater than deflection of the first drive paddle when the drive system is operating.

Abstract: A method of programming a memory includes selecting a logic state for programming a first bitcell of the memory. A first one-time-programmable (OTP) element of the first bitcell is programmed using a first set of conditions intended to achieve a first target resistance in accordance with the selected logic state which results in a first degree of programming of the first OTP element. A second OTP element of the first bitcell is programmed using a second set of conditions different from the first set of conditions intended to achieve a second target resistance in accordance with the selected logic state which results in a second degree of programming of the second OTP element, wherein the first and second degrees of programming are visually indistinguishable.

Abstract: Embodiments of a semiconductor device include a base substrate including an upper surface, a nucleation layer disposed over the upper surface of the base substrate, a first semiconductor layer disposed over the nucleation layer, a second semiconductor layer disposed over the first semiconductor layer, a channel within the second semiconductor layer and proximate to an upper surface of the second semiconductor layer, and an enhanced resistivity region with an upper boundary proximate to an upper surface of the first semiconductor layer. The enhanced resistivity region has an upper boundary located a distance below the channel. Embodiments of a method of fabricating the semiconductor device include implanting one or more ion species through the first semiconductor layer to form the enhanced resistivity region.

Abstract: A MEMS device includes a movable mass having a central region overlying a sense electrode and an opening in which a suspension structure and spring system are located. The suspension structure includes an anchor coupled to a substrate and rigid links extending from opposing sides of the anchor. The spring system includes a first and second spring heads coupled to each of the rigid links. A first drive spring is coupled to the first spring head and to the movable mass, and a second drive spring is coupled to the second spring head and to the movable mass. The movable mass is resiliently suspended above the surface of the substrate via the suspension structure and the spring system. The spring system enables drive motion of the movable mass in the drive direction and sense motion of the movable mass in a sense direction perpendicular to the surface of the substrate.

Abstract: Various embodiments relate to a method and circuit for maintaining zero voltage switching while having a fixed switching frequency, the method including switching on a first switch, on a primary side, at a beginning of a primary stroke of a time period at zero voltage and switching off the first switch at an end of the primary stroke, switching on a second switch, on a secondary side, at a beginning of a secondary stroke of a time period and switching off the second switch at an end of the secondary stoke of a time period and switching on a second switch at a beginning of a ringing period of the time period and switching off the second switch at an end of a bi-directional flyback action.

Abstract: An electronic device includes a plurality of modules coupled to a charge storage node. A method for operating the electronic device includes starting up the electronic device and entering a demonstration mode. During the demonstration mode, a demonstration is performed for a predetermined amount of time by enabling a subset of the plurality of modules. At the expiration of the predetermined amount of time, the electronic device is shut down. If the electronic device is operating in normal operating mode, the charge level of the charge storage cell can be monitored such that when it falls below a minimum charge threshold, the electronic device is shut down. The minimum charge threshold can be based on a number of demonstrations to be performed on a remaining capacity of the charge storage cell.

Abstract: A system for performing a data transaction between a memory and a master via a bus based on a strobe signal. The memory includes at least one memory bank having first and second cuts. The data transaction is either a read transaction or a write transaction. The system includes an input and output interface in communication with the master for receiving a data transaction request, an identifying unit that identifies a type of the data transaction, a control unit that selectively enables at least one of the first and second cuts based on the data transaction type, and a data processing unit that processes data to be read from or written to the enabled cut based on the data transaction type.

Abstract: Various embodiments relate to a method and apparatus for over sampling a RF carrier signal, the method including receiving, by an ADC, the RF carrier signal, sampling, by the ADC, the RF carrier signal using the selected clock signal which is at least quadruple the RF carrier signal, down sampling, by a RF-DSP, the RF carrier signal by a factor of two to generate I channel data and Q channel data, mixing down, by the RF-DSP, the I channel data and the Q channel data, and outputting, by the RF-DSP, the I channel data and Q channel data to a baseband DSP.

Abstract: A system for counting steps comprising a 3-D accelerometer is disclosed. The system also includes a pre-processor module coupled to the 3-D accelerometer and a dominant component computation unit coupled to the pre-processor module. The dominant component computation unit is configured to identify a dominant component in an output of the 3-D accelerometer. The system further includes a step counter for counting a number of steps using the output of the dominant component computation unit. The step counter includes a Fast Fourier Transform (FFT) module and a direct current (DC) remover module to remove a static component from the output of the FFT module. The step counter also includes a derivative filter and a zero crossing detector.

Abstract: Vibration gyroscope circuitry, connectable to a vibrating MEMS gyroscope, includes drive circuitry for driving the gyroscope and a measurement circuit for providing a drive measurement signal indicating displacement of a mass along a drive axis. Sense circuitry processes a sense measurement signal of the gyroscope indicating displacement of the mass along a sense axis. A digital sample clock generator includes an oscillator for generating a master clock, a counter for counting master clock periods during one period of an input signal derived from the drive measurement signal, and a number count monitor for determining during how many input signal periods the number count stays constant and for comparing a number of constant periods with a critical number of constant periods. A frequency shifter triggers the oscillator to shift the master clock frequency whenever the monitor determines that the number of constant periods exceeds the critical number of constant periods.

Abstract: A radio receiver is disclosed. The radio receiver includes an analog tuner and a baseband processor to provide radio functions. The baseband processor is coupled to the analog tuner. The radio receiver further includes a memory and a controller coupled to the analog tuner, the baseband processor and the memory. The controller is configured to perform an operation and the operation includes causing the analog tuner to scan a spectral band to identify radio stations and based on a signal matrix obtained from scanning a station in the spectral band tentatively determining if the station represents a digital radio mondiale (DRM) station and if so, storing the station in a list of possible DRM stations in the memory.

Abstract: A bridgeless power factor correction (PFC) circuit has first and second nodes, and first and second current paths connected between the first and second nodes. The first current path includes a first semiconductor device and a first switch element, and the second current path includes a second semiconductor device and a second switch element. One of the first and the second current paths further includes first and second sensing elements that are oppositely connected in series.

Abstract: A method for forming a metal oxide layer on a wafer. In some embodiments, the method includes forming a layer of a metal oxyhalide on a wafer followed by an anneal of the wafer which removes halogens from the layer to form a layer of metal oxide. A semiconductor device may be formed from the wafer.

Abstract: A sensor circuit and method. The circuit includes a first subcircuit that includes a first sense capacitor, a first integration capacitor, and a first clock input for receiving a first digital clock signal for initiating discharge of the first integration capacitor at time T. The circuit includes a second subcircuit that includes a second sense capacitor, a second integration capacitor, and a second clock input for receiving a second digital clock signal for initiating discharge of the second integration capacitor at time T+Td. A rate of discharge of the first and second integration capacitors is at least partly determined by a capacitance of the first and second sense capacitor, respectively. At time Teval, after initiation of discharge of the first and second sense capacitors, the extent to which the first and second integration capacitors have discharged is compared. A digital signal indicating the result of the comparison is outputted.