Abstract: A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The structure also includes a substrate having a cavity, wherein the cavity is defined by a vertical portion and a horizontal portion, wherein the vertical portion surrounds the first device, the horizontal portion is over the first device, and the first device is between the horizontal portion and the first major surface of the interconnect layer such that the first device is in the cavity. The structure further includes a second microelectronic device attached to the horizontal portion of the substrate, and encapsulant on the interconnect layer and surrounding the first device, the substrate, and the second device, such that the substrate is embedded in the encapsulant.

Abstract: An impedance-matching circuit includes a resonant circuit, first and second capacitors, and first through third inductive circuits. The resonant circuit includes a fourth inductive circuit connected in parallel with a capacitive circuit. The impedance-matching circuit receives a radio frequency power amplifier (RFPA) output signal, which includes first and second signals at first and second frequencies, respectively. A resonant frequency of the resonant circuit is between the first and second frequencies. The resonant circuit offers inductive and capacitive impedances to the first and second signals, respectively. The impedance-matching circuit generates a matched RFPA output signal including the first signal and the second signal, where the second signal is at a reduced voltage level.

Abstract: An integrated circuit includes an I/O pad and a protection device coupled to the I/O pad and a first supply node. A transient event detector includes a latch; a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to a first supply node, and a second current electrode coupled to a data input of the latch, wherein the latch is configured to store an indication that a transient event occurred. An event level sensor includes a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to the protection device, and a second current electrode coupled to a load circuit; a rectifier device coupled between the second current electrode and a capacitor; a second transistor having a control electrode coupled to the capacitor; and an output circuit configured to place a current on a first sense bus proportional to a current through the load circuit.

Abstract: A linear resonant actuator controller for a mobile device having a linear resonant actuator is described. The linear resonant actuator controller comprises a controller output configured to be coupled to a linear resonant actuator; an audio processor having an audio processor input and an audio processor output coupled to the controller output. The audio processor is configured to receive an audio signal comprising speech, to process the audio signal by attenuating the audio signal frequency components at the resonant frequency of the linear resonant actuator with respect to at least some other audio signal frequency components, and to output the processed audio signal on the audio processor output.

Abstract: Various aspects of the present disclosure are directed toward apparatuses, methods, and systems for presenting boosted power regulation to a load. These aspects include a power-switching circuit that selectively passes current in response to a boost-converter control circuit. A current-control circuit selectively powers the load in response to the power-switching circuit passing current.

Abstract: A wireless electrical power receiver for inductively generating alternating current power in a wireless electrical power transfer system having a transmission resonant frequency, the receiver comprising a receiver resonator having a receiver resonant frequency, the receiver resonator constructed and arranged such that the receiver resonant frequency is detuned from the transmission resonant frequency.

Abstract: A clock generator circuit includes an internal reference clock generator, a sequential circuit, and a pulse generator circuit. The internal reference clock generator circuit receives a clock buffer signal, a reset signal, and provides a first clock signal. The sequential circuit receives the first clock signal, and provides an internal reference clock signal based on the first clock signal. The pulse generator circuit receives the internal reference clock signal, a slow ring oscillator clock signal, and the reset signal. The pulse generator circuit counts a number of internal reference clock signals cycles for each cycle of the slow ring oscillator clock signal, and generates a pulse signal in response to the number being equal to zero during a cycle of the slow ring oscillator clock signal. The pulse signal toggles the flip-flop clock circuit to recover from a deadlock.

Abstract: An electronic device may include: a load and a voltage regulator coupled to the load and configured to provide a load current, where the voltage regulator includes a first and a second pass device coupled in parallel and configured to operate simultaneously. A method may include providing current to a load using a first and a second pass device coupled in parallel and configured to operate simultaneously, where the first device provides a first current corresponding to a high-frequency component and the second device provides a second current corresponding to a low-frequency component; in response to a decrease in a low-frequency component, causing the second current to decrease and causing the low-frequency component to increase; and in response to an increase in the low-frequency component, causing the second current to increase and causing the low-frequency component to decrease.

Abstract: A decimation filter including a Hadamard-Walsh transform circuit, a comparator, and an inverse Hadamard-Walsh transform circuit. The Hadamard-Walsh transform circuit includes an input receiving a pulse density modulation bitstream and an output providing a stream of digital samples. The comparator replaces each digital sample that has a magnitude below a predetermined threshold value with a zero value and provides adjusted digital samples. The inverse Hadamard-Walsh transform circuit has an input receiving the adjusted digital samples and has an output providing pulse code modulation data values. The decimation filter may further include a down-sampler that down samples the adjusted digital samples by before being provided to the inverse Hadamard-Walsh transform circuit. The decimation filter may include a low pass filter and another down-sampler at the output.

Abstract: As may be consistent with one or more embodiments, an apparatus and or method involves a switching power supply circuit and a control circuit therefor. The switching power supply circuit operates in high and low-power modes. In the high power mode, high and low power rails of a first circuit and of a second circuit are coupled to a power source circuit (e.g. a battery). In the low-power mode, the first circuit is operated in a high power domain and the second circuit is operated in a low power domain using recycled charge from the high power domain. The control circuit operates the switching circuit in the high-power mode and low-power mode (for power conservation) in response to a control signal.

Abstract: A method performed by a radio base station, the method including determining a link configuration of a first communication link, the first communication link being a current communication link between a first radio equipment control (REC) device and a radio equipment (RE) device. The method further including in response to determining that a second communication link between a second REC device and the RE device is to replace the current communication link, instead of the first communication link, establishing, by the second REC device, the second communication link based on the determined link configuration of the first communication link.

Abstract: Embodiments of a saturation controller for a flyback switched-mode power supply (SMPS) and a method for saturation control for a flyback SMPS involve measuring a length related to a primary stroke in the flyback SMPS, comparing the length related to the primary stroke to a length related to a previous primary stroke in the flyback SMPS to generate a comparison result and adjusting a switching period time of the flyback SMPS based on the comparison result such that saturation of the flyback SMPS is reduced.

Abstract: According to the present disclosure, there is provided methods of processing a signal using quantized symbols. More particularly, in one example, the method comprises the steps of processing a signal (206), said method comprising the steps of: receiving a signal (206) comprising a plurality of raw symbols, each raw symbol having a plurality of bits and being conveyed in a channel; estimating a channel state information value (206) of the channel used to convey each raw symbol to generate a corresponding plurality of channel state information values; quantizing the plurality of raw symbols based on their channel state information values to generate a sequence of quantized symbols (214); and quantizing the channel state information values to generate a sequence of quantized channel state values (216).

Abstract: A through substrate via (TSV) and method of forming the same are provided. The method of making the TSV may include etching a via opening into the backside of semiconductor substrate, the via opening exposing a surface of a metal landing structure. A conductive layer is deposited over the backside of semiconductor substrate, sidewalls of the via opening, and exposed surface of the metal landing structure. The conductive layer is coated with a polymer material, filling the via opening. The polymer material is developed to remove the polymer material from the backside of semiconductor substrate, leaving the via opening filled with undeveloped polymer material. A planar backside surface of semiconductor substrate is formed by removing the conductive layer.

Abstract: The present application relates to a circuit arrangement for sensing a current. The circuit arrangement comprises a current sense circuit configured to cause the sense current through a sense transistor, wherein the sense current is representative of a load current through a load transistor. The current sense circuit comprises a differential difference amplifier with a first differential input terminal pair coupled across the drain electrode and the source electrode of the load transistor and a second differential input terminal pair coupled across the drain electrode and the source electrode of the sense transistor. The current sense circuit is operable to force the same voltage difference value across the drain electrode and the source electrode of the load transistor as across the drain electrode and the source electrode of the sense transistor.

Abstract: A memory system includes a memory array, control circuitry, and comparator circuitry. The memory array includes a first section having a first plurality of programmed bitcells having a first threshold voltage distribution and a second section having a second plurality of programmed bitcells having a second threshold voltage distribution which has a lower average threshold voltage than the first threshold voltage distribution. The first plurality and second plurality of programmed bitcells are programmed with a same set of data values. The control circuitry is configured to provide a read request to the memory array and receive read data in response to the read request, wherein the read data comprises first read data from the first section and second read data from the second section. The comparator circuitry is configured to compare the first read data to the second read data and generate an error indicator in response to the compare.

Abstract: A method of making a semiconductor switch device and a semiconductor switch device made according to the method. The method includes depositing a gate dielectric on a major surface of a substrate. The method also includes depositing and patterning a gate electrode on the gate dielectric. The method further includes depositing an oxide to cover the top surface and sidewall(s) of the gate electrode. The method also includes, after depositing the oxide, performing a first ion implantation process at a first implantation dosage for forming a lightly doped drain region of the switch device. The method further includes forming sidewall spacers on the sidewall(s) of the gate electrode. The method also includes performing a second ion implantation process at a second implantation dosage for forming a source region and a drain region of the semiconductor switch device. The second implantation dosage is greater than the first implantation dosage.

Abstract: Input/output circuitry includes a first PMOS device and a first NMOS device having first current electrodes are connected to each other and a pad. First selection circuitry, when the I/O circuitry is disabled, provides a first supply voltage to a control electrode and an N-well of the first PMOS device when the pad voltage is between the first and second supply voltages and to directly provide the pad voltage to the control electrode and the N-well of the first PMOS device when the pad voltage is greater than the first supply voltage. Similarly, second selection circuitry, when the I/O circuitry is disabled, provides a second supply voltage or directly provides the pad voltage to a control electrode and a P-well of the first NMOS device depending on whether the pad voltage is between the first and second supply voltages or less than the second supply voltage, respectively.

Abstract: A method for facilitating network joining is disclosed, wherein, while a communication session is active between a network gateway and an NFC device comprised in or connected to a networkable device, the following steps are performed: the network gateway obtains a first cryptographic key associated with the networkable device; the network gateway encrypts, using said first cryptographic key, a network key associated with a network; the network gateway provides the encrypted network key to the networkable device, such that the networkable device may decrypt the encrypted network key using a second cryptographic key. Furthermore, a corresponding computer program product and a corresponding system for facilitating network joining are disclosed.

Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.