Abstract: A device configured for tracking spatial placement of one or more HF (High frequency) RFID (Radio-frequency identification) tag objects on a surface is disclosed. The device includes an HF RFID reader, a transmission antenna, and a plurality of reception antennas. The transmission antenna effectively transmits power and data over an area that is defined to be a detection surface. Each one of the plurality of reception antennas is able to effectively receive data from a separate portion of the detection surface, while all of the plurality of reception antennas together are able to effectively receive data from substantially all of the detection surface. In one embodiment, the transmission antenna is constantly transmitting power.

Abstract: An on-die temperature sensor measures temperature during a temperature-measurement session. A PTAT (proportional-to-absolute-temperature) generator generates an analog PTAT voltage that is dependent on temperature. A ramp generator generates a changing, analog ramp voltage whose rate of change is dependent on the PTAT voltage, such that the rate of change of the ramp voltage is dependent on the temperature. A comparator compares the ramp voltage to a reference voltage to detect termination of the temperature-measurement session. A counter generates a count value based on the duration of the temperature-measurement session, where the count value is mapped to the measured temperature using a lookup table. The PTAT generator has (i) two npn-type bipolar devices that generate a base-to-emitter voltage difference that is dependent on temperature and function as an amplifier input stage and (ii) circuitry to generate base currents for the bipolar devices to avoid current loading at the PTAT output.

Abstract: A receiver system includes an automatic gain control (AGC) module configured to control a first gain control signal to a first gain element having variable gain control. The receiver system also includes a DC (direct current) offset correction block coupled to the AGC module, the DC offset correction block configured to trigger the AGC module to output a set of calibration gain control signals to the first gain element and capture a set of DC offset measurements of a first signal received at the DC offset correction block, where the first signal is passed by the first gain element. The DC offset correction block is further configured to estimate one or more DC offset components using the set of DC offset measurements, and calculate a first correction control signal corresponding to a first gain level of the first gain element using the one or more DC offset components.

Abstract: A driver circuit for an integrated circuit (IC) is configurable to operate in three different signaling modes, namely, differential signaling mode, single-ended current mode, and single-ended voltage mode. The driver circuit receives first and second input signals from a pre-driver and outputs first and second output signals that conform with the selected one of the three signaling modes.

Abstract: A system includes a tire pressure monitoring system (TPMS) module coupled with a wheel on a vehicle and a vehicle navigation system of the vehicle. A method entails determining a movement signal at the TPMS module and receiving the movement signal at the vehicle navigation system. The vehicle navigation system includes an inertial sensor system configured to supply motion signals indicative of motion of the vehicle and the vehicle navigation system determines output data in response to the motion signals. The vehicle navigation system output data is calibrated at the vehicle navigation system by utilizing movement signals from the TPMS module to remove an error component from the vehicle navigation system output data. Thus, calibration can be performed in lieu of or in addition to utilizing signals from satellites, which may not be available at all times.

Abstract: Antenna, including: a first conductive structure having a first end coupled to a conductive strip and a second end; wherein the conductive strip is coupled to a first feed point; a second conductive structure having a first portion and a second portion; wherein the second portion is coupled to a second feed point; wherein the second end of the first conductive structure is separated from the first portion of the second conductive structure by a gap; wherein the first conductive structure is substantially in parallel with and has a different width than the first portion of the second conductive structure; wherein the first conductive structure is configured to carry current in a first polarity and the first portion of the second conductive structure is configured to carry current in a second polarity opposite to the first polarity; and wherein the feed points are configured to carry an RF signal.

Abstract: A wireless transmitter wirelessly charges/powers a wireless receiver. The transmitter performs an analog ping to tentatively detect a device. During an energizing phase of the analog ping, the transmitter applies power pulses to a resonant circuit within the transmitter, where, after application of the power pulses, the resonant circuit enters a free-resonance state of a resonating phase of the analog ping that follows the energizing phase. During the resonating phase, while the resonant circuit is in the free-resonance state, the transmitter samples voltage within the resonant circuit to generate one or more voltage-level samples. The transmitter processes the voltage-level samples to tentatively detect the device. If a device is tentatively detected then the transmitter performs a digital ping to definitively determine whether the device is present. If definitively detected then the transmitter wirelessly charges/powers the wireless receiver.

Abstract: A recess is formed at a semiconductor layer of a device to define a plurality of mesas. An active trench portion of the recess residing between adjacent mesas. A termination portion of the trench residing between the end of each mesa and a perimeter of the recess. The transverse spacing between the mesas and the lateral spacing between the mesas and an outer perimeter of a recess forming the mesas are substantially the same. A shield structure within the trench extends from the region between the mesas to the region between the ends of the mesas and the outer perimeter of the recess forming the mesas. A contact resides between a shield electrode terminal and the shield portion residing in the trench.

Abstract: An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. A first current conducting terminal of a transistor is electrically coupled to the first conductive feature. Second and third conductive features may be coupled to other regions of the bottom substrate surface. A first filter circuit includes an inductor formed over a portion of the top substrate surface that is directly opposite the conductor-less region. The first filter circuit may be electrically coupled between a second current conducting terminal of the transistor and the second conductive feature. A second filter circuit may be electrically coupled between a control terminal of the transistor and the third conductive feature. Conductive leads may be coupled to the second and third conductive features, or the second and third conductive features may be coupled to a printed circuit board.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.

Abstract: A display controller comprises a plurality of channels for fetching data from a memory, a plurality of buffers coupled to the channels for receiving the fetched data from the channels, a buffer controller for controlling the buffers and the channels, and a processing unit coupled to the buffers, the display and buffer controller for receiving the data from the buffers, outputting a control signal to the display based on the received data, and controlling the buffer controller, respectively. Each buffer has a respective fixed memory capacity for storing the fetched data. The processing unit activates layers in the output image for displaying an output image on the display. The channels correspond to associated layers. The buffer controller adds to the respective fixed memory capacity of a particular buffer associated to an activated layer, one further fixed memory capacity of at least one further buffer associated to an inactive layer.

Abstract: A method and apparatus are provided for detecting a rotor lock condition in a sensorless permanent magnet synchronous motor. A BEMF observer determines an estimated rotor speed {circumflex over (?)} and a first BEMF voltage value in an estimated rotor-related ?,? reference frame. In addition, a second estimated BEMF voltage value is calculated in a rotor-related d,q reference frame based on at least a first motor constant and an estimated rotor speed {circumflex over (?)}. After generating a BEMF error filter value from the first and second estimated BEMF voltage values and calculating a BEMF error threshold value as a function of the estimated rotor speed {circumflex over (?)} that is subject to a minimum threshold BEMF value, a rotor lock condition is detected based on at least the BEMF error filter value and the BEMF error threshold value.

Abstract: This disclosure describes a library optimization system that creates modified standard cells with reduced leakage currents that meet predefined cell area, timing, and leakage requirements. The library optimization system selects transistors to upsize based upon the fact that transistors of a same type, such as p-channel or n-channel transistors, that are connected in series produce a small reverse bias between the gate and source, known as a stacking effect. The stacking effect results in an inherent decrease in leakage current for the series-connected transistor chain. As such, the library optimization system adjusts gate lengths of transistors that are not part of the transistor series chains having a relatively large amount of same type transistors.

Abstract: A semiconductor device and method. The device includes a first domain and a second domain each having a power rail and a ground rail. The device further includes a signal line connected between the first domain and the second domain. The device also includes an electrostatic discharge protection circuit for providing cross-domain ESD protection. The protection circuit includes a blocking transistor connected between the first domain power rail and the signal line. The protection circuit also includes a power rail clamp connected between the first domain power rail and the first domain ground rail. The power rail clamp is operable to apply a control signal to a gate of the blocking transistor to switch it on during normal operation and to switch it off during an ESD event. The power rail clamp is operable during the ESD event to conduct an ESD current.

Abstract: An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first supply voltage, a second detection circuit coupled to a second supply voltage, and a rail clamp device. During a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit. During a second type of electrical stress event, the rail clamp device is activated in response to a second output signal provided by the second detection circuit.

Abstract: An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a lateral side of the package, and methods of making the semiconductor device package.

Abstract: A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.

Abstract: A system-on-chip (SOC) includes a compensation circuit that compensates for PVT variations of the SoC and an external memory connected to the SOC. The compensation circuit includes first through third delay calculators, first through third delay circuits, first through third latches, first and second comparators, and a delay control circuit. The delay calculators generate first through third delay count data. The delay circuits use three delay counts to generate first through third clock signals. The latches receive data stored in the external memory, and output start-point, mid-point, and end-point data, respectively. The first and second comparators generate increment or decrement signals based on the start-point, mid-point and end-point data comparisons. The delay control circuit generates modified first delay count data, which along with the first through third delay count data, compensate for the PVT variations of the SoC and the external memory.

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

Abstract: A method for implementing a host card emulation (HCE) service in a remote near field communication (NFC) device is provided. In the method, a first command application protocol data unit (APDU) is received at the remote NFC device from an NFC reader. A first response to the first command APDU is computed. A second command APDU from the NFC reader is predicted that is likely to follow receipt of the first command APDU from the NFC reader. A second response to the predicted second command APDU is computed. A third command APDU is received from the NFC reader. It is determined if the prediction of the second command APDU matches the third command APDU. If the second and third command APDUs match, then the computed second response is send directly to the NFC reader without having to traverse a NFC stack.