Abstract: Embodiments of a wireless communication unit and operation of such unit in a test mode are provided, where a wireless communication unit includes: transmit and receive path circuitry coupled to an antenna via a switch; which is operated to: close the switch to connect the transmit path circuitry to the antenna, wherein the receive path circuitry remains unconnected, activate the transmit path circuitry to transmit an RF test signal on the antenna, wherein the RF test signal couples across the switch as a leakage signal, activate the receive path circuitry concurrently as the RF test signal is transmitted, wherein the receive path circuitry provides the leakage signal to an RF to DC converter via a directional coupler, and wherein the RF to DC converter is configured to generate an error signal that indicates whether an error has been detected in the receive path circuitry.

Abstract: Embodiments of a lead frame for a packaged semiconductor device are provided, one embodiment including: a die pad; a first row of active lead fingers that are laterally separated from one another along their entire length; a package body perimeter that indicates placement of a package body of the packaged semiconductor device, wherein the package body perimeter is located laterally around the die pad; a first dummy lead finger positioned in parallel next to an initial active lead finger of the first row of active lead fingers, wherein the first dummy lead finger and the initial active lead finger are laterally separated from one another along their entire length, and wherein the first dummy lead finger is separated from the package body perimeter by a gap distance; and a first tie bar connected to an outside edge of the first dummy lead finger.

Abstract: An ESD protection structure formed within an isolation trench and comprising a first peripheral semiconductor region of a first doping type, a second semiconductor region of the first doping type, and a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the semiconductor regions of the first doping type and isolation between the further semiconductor region of the first doping type and the isolation trench. The semiconductor structure of the second doping type is formed such that no semiconductor region of the second doping type is formed between a peripheral side of the first semiconductor region of the first doping type and a wall of the isolation trench, and no semiconductor region of the first doping type is in contact with the isolation trench other than the first semiconductor region of the first doping type.

Abstract: The disclosure relates to a temperature-controlled oscillator.

Abstract: Task context information is transferred concurrently from a processor core to an accelerator and to a context memory. The accelerator performs an operation based on the task context information and the context memory saves the task context information. The order of transfer between the processor core is based upon a programmable indicator. During a context restore operation information is concurrently provided to data bus from both the accelerator and the processor core.

Abstract: A memory system includes a main memory array, a redundant memory array, and a content addressable memory (CAM). The CAM includes a plurality of entries, wherein each entry includes a plurality of column address bits and a plurality of maskable row address bits. When an access address for a memory operation matches an entry of the CAM, the memory system is configured to access the redundant memory array to perform the memory operation.

Abstract: A digital to analog converter (DAC) circuit includes pulse generator circuit for generating voltage pulses having a predetermined length and shape. The voltage pulses are used to control the generation of current pulses generated by a voltage to current converter. The voltage to current converter includes a set of switchable resistors where the resistance value provided by the set is dependent upon a digital value of a digital signal. In some embodiments, the current amplitude of the current pulses is dependent upon the resistance value and is indicative of the digital value.

Abstract: The embodiments described herein provide microelectromechanical systems (MEMS) devices, such as three-axis MEMS devices that can sense acceleration in three orthogonal axes (e.g., x-axis, y-axis, and z-axis). In general, the embodiments described can provide decoupling between the sense motions of all three axes from each other. This decoupling is facilitated by the use of an inner frame, and an outer frame, and the use of rotative spring elements combined with translatory spring elements that have asymmetric stiffness. Specifically, the translatory spring elements facilitate translatory motion in two directions (e.g., the x-direction and y-direction) and have an asymmetric stiffness configured to compensate for an asymmetric mass used to sense in the third direction (e.g., the z-direction).

Abstract: A mechanism is provided for debugging of system-wide packet loss issues in network devices by automatically identifying packet loss conditions at runtime of the network device and by logging and analyzing relevant data to help diagnose the issues resulting in lost packets. A network programmer defines a path through the communications processor that identified packets should follow, and then hardware mechanisms within the modules of the communications processor are used to determine whether the packets are indeed following the defined path. If not, then the hardware mechanisms halt processing and logging being performed by all or part of the communications processor and provide logged information and packet information to an analysis tool for display. In this manner, debugging information can be provided in real time, along with a history of the packet's progress through the communication processor stages.

Abstract: A radar device includes a RF signal source, two or more antenna interface units, a feed network, and a control unit. The RF signal source is arranged to provide a RF signal; each of the antenna interface units includes an antenna port and one of the following: an amplifier and a mixer; the feed network includes two or more buffers, each buffer has an active and an inactive state; the control unit is arranged to generate or receive a selection signal which specifies none, one, or more of the antenna interface units as active antenna interface units and the remaining antenna interface units as inactive antenna interface units; the control unit is arranged to activate and deactivate the buffers in dependence on the selection signal so as to feed the RF signal to the none, one, or more active antenna interface units and not to the inactive antenna interface units.

Abstract: In a pipelined element configured to execute multiple contexts and including an instruction pipeline and a plurality of context modules each having a register file and a functional unit, a method includes scheduling a first context for execution in the instruction pipeline. The instruction pipeline includes an execution unit having a plurality of functional units. Each functional unit of the plurality of functional units is configured to execute instructions of a scheduled context of the plurality of contexts. A first instruction of the first context which precedes an instruction loop of the first context is executed. In response to executing the first instruction, the first context is released from being scheduled for execution in the instruction pipeline and execution of the first context is continued using a first context module. The first context module includes a context-specific functional unit configured to execute the instruction loop.

Abstract: An integrated circuit for saturation detection comprises: a plurality of gain components; a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components; a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors; and a controller operably coupled to the plurality of logic elements. The controller is arranged to apply a signal to a second input of individual ones of the plurality of logic elements such that an output of the respective logic element identifies a saturation event of the saturation detector associated with that respective logic element.

Abstract: According to a first aspect of the present disclosure, an electronic device is provided, which comprises a light-emitting diode arrangement and a driver arrangement operatively connected to the light-emitting diode arrangement, wherein at least one light-emitting diode of the light-emitting diode arrangement is operatively connected between a first driver of the driver arrangement and a second driver of said driver arrangement, such that, in operation, the light-emitting diode may be energized with current flowing between the first driver and the second driver. Furthermore, according to a second aspect of the present disclosure, a corresponding method of manufacturing an electronic device is conceived.

Abstract: A processor system includes at least two processor cores and an interrupt controller including interrupt priority registers configured for registering interrupt priorities of the respective processor cores. The processor system further includes at least two task timers associated with respective processor cores. Each task timer includes a counter configured for producing a counter value, a timeout value register configured for storing a timeout value and a tidemark value register configured for storing a tidemark value smaller than the timeout value. Each task timer is configured for producing a timeout signal when the counter value equals the timeout value and for producing a tidemark signal when the counter value equals the tidemark value. The interrupt controller is configured for increasing the interrupt priority of a processor core in response to a tidemark signal and for decreasing the interrupt priority of a processor core in response to a timeout signal.

Abstract: An electronic device has terminals for interfacing internal signals to other electronic devices. Each terminal is electrically coupled to a terminal driver and a terminal control circuit for receiving a terminal configuration defining the properties and multiplexing of the terminal. The actual configuration of the terminal driver is set according to the terminal configuration. The device has at least one terminal checker arranged for comparing the actual configuration to at least one check configuration, the check configuration defining a configuration of the terminal driver that is either allowed or not allowed, and for, when said comparing indicates a not allowed configuration, setting the actual configuration to a default configuration. Advantageously safe operation of the device in a system is achieved by monitoring the configuration of the multiplexed terminals, and switching to a default configuration when in error.

Abstract: A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.

Abstract: In an analog-to-digital converter (ADC) having storage capacitors, active, top-plate, n-type, switch circuitry has an n-type transistor and gate-voltage control circuitry that generates the gate voltage to turn on and off the transistor. The control circuitry turns off the transistor by generating the gate voltage at a level that limits the gate-to-source voltage difference, thereby limiting GISL leakage current through the transistor that can otherwise jeopardize the accuracy of the ADC digital output value. In one implementation, when the transistor is to be off (for example, during the ADC conversion phase), the control circuitry generates the gate voltage to be at ground if the source voltage is below a reference voltage, and above ground if the source voltage is above the reference voltage. The switch circuitry can also be implemented using a p-type device or a transmission gate instead of the n-type device.

Abstract: An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device.

Abstract: A method, system, and apparatus are provided for managing multiple DMA channels in different DMA modes by processing command sequences associated with different virtual DMA channels and stored in a command queue structure, such that a first command sequence is processed to directly configure one or more first register descriptors at a context store to implement a direct configuration DMA mode for a first virtual channel, a second command sequence is processed to initiate a fetch of a linked list descriptor chain for loading one or more second register descriptors at a second DMA channel context store register to implement a link list configuration DMA mode for a second virtual channel, and a third command sequence is processed to retrieve an instruction program for loading into the command queue structure and execution by the DMA controller to implement a program configuration DMA mode for a third virtual channel.

Abstract: A FlexRay network guardian including: a resetting leading coldstart node (RLCN) detector configured to detect a RLCN failure; a deaf coldstart node (DCN) detector configured to detect a DCN failure; a babbling idiot (BI) detector configured to detect a BI failure; and a FlexRay network decoder configured to output a signal regarding the status of the FlexRay network to the RLCN detector, DCN detector, and BI detector, wherein the RLCN detector, DCN detector, and BI detector are configured to send an indication of a failure to a containment module.