Abstract: An integrated circuit has at least two power domains. A first power domain has circuitry coupled between a first power supply terminal and a second power supply terminal. A second power domain has circuitry coupled between a third power supply terminal and a fourth power supply terminal. A complementary voltage regulator includes N-type and P-type voltage regulators. The N-type voltage regulator is coupled between the first and third power supply terminals and controls a first voltage level at the second power supply terminal. The P-type voltage regulator is coupled between the third and fourth power supply terminals and controls a second voltage level at the third power supply terminal. The N-type voltage regulator produces a mid-level supply voltage to the P-type regulator and a “ground” for the circuits in the first power domain. The P-type regulator circuit produces a “ground” for the N-type regulator and a mid-level supply voltage for the circuits in the second power-domain.

Abstract: Embodiments of a noise-shaping crest factor reduction method for a carrier signal (and a device that performs the method) include (a) clipping the carrier signal by selecting at least one carrier signal peak that has a magnitude exceeding a predetermined crest factor reduction threshold, (b) subtracting the resulting clipped signal from the carrier signal, (c) confining, by a noise shaping filter, the resulting clipping noise signal in a frequency band corresponding to that of the carrier signal, and (d) subtracting the resulting spectrally shaped clipping noise signal from a delayed version of the carrier signal. The confining process includes selecting first sub-areas of the noise shaping filter response at one or more guard bands, selecting at least one second sub-area of the noise shaping filter response elsewhere in the frequency band, and setting the first sub-areas to a first predetermined magnitude higher than the magnitude of the second sub-area.

Abstract: A semiconductor device assembly includes an interposer having an opening extending from a first major surface to a second major surface of the interposer and a plurality of external connectors on the second major surface. The first major surface of the interposer is attached to a packaged semiconductor device. The opening of the interposer exposes the packaged semiconductor device.

Abstract: A method of obscuring software code implementing an elliptic curve cryptography (ECC) point multiplication function, including: receiving ECC parameters including a multiplier d having N bits; transforming multiplier d into an array d(i) with ?1, 0, and +1 values while maintaining the same value for d; and generating ECC point multiplication function operations using the transformed multiplier array d(i) and N, wherein the generated ECC point multiplication function operations are split variable operations.

Abstract: In one or more embodiments, one or more systems, method, and/or processes described herein can change/switch from a first trace mode to a second trace mode without halting a system under development and/or under test. For example, a debug/trace unit can switch a trace mode without halting a processing unit of a system under development and/or under test. For instance, a debug/trace unit can switch a trace mode that can occur on a change of flow boundary of program instructions executable by a processing unit, at a branch instruction, if a region of program instructions is entered or exited, and/or if a capacity of a buffer changes. In one or more embodiments, Nexus messages can be utilized, and trace mode switches can include switches to and/or from traditional and history traces modes.

Abstract: An apparatus for reception and detection of RACH data in an LTE input signal includes a hardware accelerator that has a decimator that filters and down-samples the input signal, a first Fourier transform circuit that transforms the decimated signal from the time domain to the frequency domain, and a second transform circuit that multiplies the resulting signal by a complex Z-C sequence and performs an inverse Fourier transform (iFT) operation to transform the multiplied signal from the frequency domain to the time domain. A DSP performs a delay profile analysis operation on the signal resulting from the iFT operation.

Abstract: The present application relates to a Common Public Radio Interface, CPRI, lane controller and a method of operating thereof. The CPRI lane controller comprises a transaction counter, a symbol counter and a comparator. The transaction counter is provided for maintaining a current aggregated transactions' size, Sizetrans, representative of an accumulated size of DMA transactions performed by a DMA controller in response to symbols transferred on a CPRI link from or to the CPRI lane controller. The symbol counter is provided for maintaining a current aggregated expected symbols' size, Sizeexp, representative of an accumulated size of a sequence of transferred symbols and a currently transferred symbol. The comparator is configured to issue a symbol awareness signal, SAS, in case the current aggregated transactions' size, Sizetrans, exceeds the current aggregated expected symbols' size, Sizeexp.

Abstract: A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a common-mode reference voltage generation circuit uses one or more additional sampling switched capacitors to selectively couple the first and second reference voltages to the amplifier input during the gain phase when the input voltage is between the high and low threshold voltages using a switching configuration of switches that are controllable to connect the sampling switched capacitors to the one or more central nodes in the sampling phase, and to connect the amplifier output in feedback to the input sampling circuit in the gain phase while simultaneously connecting the one or more central nodes to the first amplifier input.

Abstract: Apparatus (110) for configuring network equipment or devices (101a-101n) during runtime is particularly applicable to network equipment based on QorIQ (trade mark) communication platforms for DPAA (Data Path Acceleration Architecture) optimization purposes and provides a way maintaining an optimal configuration which can change over time acccording to real traffic conditions. The invention may be implemented with any kind of adaptation algorithm for targeting different DPAA features. A flow characteristic function is determined from collected traffic statistics for a multiplicity of traffic flows classified by a common property such as protocol or destination or source. Flow properties are characterized over time, past present and future prediction and in relation to other existing flows based on assigned priorities. A computed flow characteristic function represents the basis for all adaptation algorithms which may be implemented in order to optimize the various DPAA features.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type. A gate structure is supported by a surface of the semiconductor substrate, and a current carrying region (e.g., a drain region of an LDMOS transistor) is disposed in the semiconductor substrate at the surface. The device further includes a drift region of a second, opposite conductivity type disposed in the semiconductor substrate at the surface. The drift region extends laterally from the current carrying region to the gate structure. The device further includes a buried region of the second conductivity type disposed in the semiconductor substrate below the current carrying region. The buried region is vertically aligned with the current carrying region, and a portion of the semiconductor substrate with the first conductivity type is present between the buried region and the current carrying region.

Abstract: A multiple-stage RF amplifier and a packaged amplifier device include driver and final-stage transistors, each having a control terminal, a first current-carrying terminal, and a second current-carrying terminal. The control terminal of the final-stage transistor is electrically coupled to the first current-carrying terminal of the driver transistor. The amplifier further includes an inter-stage circuit coupled between the first current carrying terminal of the driver transistor and a voltage reference node. The inter-stage circuit includes a first inductance, a first capacitor, and a second capacitor. The first inductance and the first capacitor are coupled in series between the first current carrying terminal and the voltage reference node, with an intermediate node between the first inductance and the first capacitor. The second capacitor has a first terminal electrically coupled to the intermediate node and a second terminal electrically coupled to the voltage reference node.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a first bipolar device connected to a first node, a second bipolar device connected to the first bipolar device and to a second node, and a metal-oxide-semiconductor (MOS) device connected to the first and second nodes and to the first and second bipolar devices and configured to shunt current in response to an ESD pulse received between the first and second nodes. The first bipolar device, the second bipolar device, and the MOS device are formed on a deep well structure. Other embodiments are also described.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes three or more bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes and a diode connected in series with the three or more bipolar transistors and one of the first and second nodes. Each of the three or more bipolar transistors includes a collector comprising collector components, an emitter comprising emitter components, and a base structure comprising a substrate region or an active region. The emitter components are alternately located with respect to the collector components. The substrate region or the active region surrounds the collector components and the emitter components. Other embodiments are also described.

Abstract: A wireless charging receiver operates on a resonance principle and includes an impedance matching circuit coupled between an antenna and a rectifier circuit. The impedance matching circuit has both series-connected and parallel-connected capacitors. At least one of the capacitors is a tunable variable capacitor. A method is provided for automatically adjusting a capacitance value of the at least one variable capacitor based on an error voltage between a target rectifier voltage and a measured rectifier voltage. Automatically adjusting the antenna impedance of the receiver provides for improved power transfer efficiency for changing operating conditions. In one embodiment, one or more of the parallel-connected capacitors are variable capacitors. In another embodiment, one or more of the series-connected capacitors are variable capacitors.

Abstract: A method for determining a distance between a device and an object, the method comprising: emitting an acoustic reference signal from a speaker of the device; receiving an acoustic input signal at a microphone of the device, the acoustic input signal including a measurement portion including a reflection of the acoustic reference signal off the object; cross correlating at least the measurement portion with the emitted acoustic reference signal to provide a cross correlated signal; receiving information relating to the object; extracting a section of the cross correlated signal corresponding to reflection of the acoustic reference signal by the object, based on the received information; analyzing the extracted section of the cross correlated signal to determine a time of flight between emitting the acoustic reference signal and receiving the reflection; and determining the distance between the device and the object based on the determined time of flight and known characteristics of the acoustic reference sign

Abstract: A circuit includes first, second, and third power supply terminals. The circuit includes an input node coupled to receive a negative voltage and an output node coupled to provide a positive voltage proportional to the negative voltage. The circuit includes a voltage-to-current converter coupled to the first power supply terminal and the input node and configured to generate an intermediate current proportional to the negative voltage at the input node. The circuit also includes a current mirror coupled to the second power supply terminal and third power supply terminal and configured to mirror the intermediate current through a first resistor to provide the positive proportional voltage.

Abstract: An integrated circuit includes a first device having a first threshold voltage (Vt) adjusting implant extension region having a first conductivity type and extending from a first implant rail region under an entirety of a first channel region. The first implant rail region and first Vt adjusting implant extension region are contiguous, and the first channel region is over an insulating layer and the insulating layer is over the first implant rail region and first Vt adjusting implant extension region. A second device has a second Vt adjusting implant extension region having the first conductivity type and extending from a second implant rail region under an entirety of a second channel region. The second implant rail region and second Vt adjusting implant extension region are contiguous, and the second channel region is over the insulating layer and the insulating layer is over the second implant rail region and second Vt adjusting implant extension region.

Abstract: A near field communication (NFC) reader is disclosed. The NFC reader includes a NFC controller, an antenna, a filter coupled to the NFC controller, a tuner coupled to the antenna and a dynamic power control unit coupled between the filter and the tuner. The dynamic power control unit includes a voltage controlled capacitor and a direct current (DC) part extraction circuit coupled to the voltage controlled capacitor.

Abstract: An embedded component package includes an embedded component substrate. The embedded component substrate includes an electronic component having an active surface including bond pads and a package body encapsulating the electronic component. The package body includes a principle surface coplanar with the active surface, A localized redistribution layer (RDL) dielectric layer is on the active surface. A localized RDL conductive layer is on the localized RDL dielectric layer and is coupled to the bond pads through openings in localized RDL dielectric layer. A primary RDL dielectric layer encloses the entire embedded component substrate and directly contacts the localized RDL dielectric layer, the localized RDL conductive layer, and the principal surface of the package body. The localized RDL conductive layer provides additional space for routing of additional interconnects while the localized RDL dielectric layer acts as a stress buffer.

Abstract: A receiver circuit comprising a first-input-terminal configured to receive an analog-input-signal, which is representative of audio-data; and a second-input-terminal configured to receive a digital-input-signal, which is representative of the same audio-data as the analog-input-signal. The receiver circuit also includes a noise-estimator configured to determine a noise-signal that is representative of a difference between the analog-input-signal and the digital-input-signal; and a de-noiser that is configured to determine a de-noised-signal by applying a de-noising algorithm to the analog-input-signal based on the noise-signal.