Abstract: A silicon controlled rectifier (SCR) circuit is configured to shunt electrostatic discharge (ESD) current from a node to a reference voltage. The SCR circuit includes a first bipolar PNP transistor having a first emitter connected to the node, a first base, and a first collector. A second bipolar NPN transistor has a second collector sharing a first region with the first base, a second base sharing a second region with the first collector, and an emitter electrically connected to the reference voltage. A guard region is configured and arranged to delay triggering of the SCR circuit in response to an ESD event by impeding current flow in the second region.

Abstract: One example discloses a watchdog circuit: wherein the watchdog circuit is configured to receive a primary ground from a primary power supply, and a backup ground from a backup power supply; wherein the watchdog circuit includes a ground switch coupled to the primary ground and the backup ground; and wherein the ground switch is configured to isolate the primary ground from the backup ground in response to a fault signal.

Abstract: An integrated circuit includes a one-time programmable (OTP) memory having a plurality of pages and address translation circuitry. A first line of each page is configured to store error policy bits. When a first bit of the first line has a first value, the page is configured to store data with error correction code (ECC) bits, and when the first bit has a second value, at least a portion of the page is configured to store data with redundancy. The address translation circuitry is configured to, in response to receiving an access address, use the first line of an accessed page of the plurality of pages accessed by the access address to determine a physical address in the accessed page which corresponds to the access address.

Abstract: A server board includes first and second devices. A first service processor of the first device operates as a master baseboard management controller of the server board, and monitors a communication channel for alive messages from a plurality service processors. A second service processor operates as a secondary baseboard management controller, and sets a second timer to a first value. In response to a determination that the second timer has expired based on a first value: the second service processor to start a switchover process, and to set the second timer to a second value based on an alive message period. In response to a primary alive message not being received from the first service processor prior to the second timer expiring based on the second value, the second service processor to reset first service processor and to operate as the master baseboard management controller.

Abstract: One example discloses a voltage regulator, including: a power supply input; a regulated voltage output; an output transistor coupled to the power supply input and the regulated voltage output; and a current amplifier coupled between the power supply input and the regulated voltage output; wherein the current amplifier is configured to supply a second current from the power supply input to the regulated voltage output when a first current between the power supply input and the output transistor exceeds a threshold current.

Abstract: Consistent with an example embodiment there is an electromagnetic induction field communication system, illustratively, for communicating on or around the body. Two transceivers (or receiver and transmitter) contain coils and capacitors suitable for generating an electromagnetic induction field surrounding the body and are capable of communicating therebetween.

Abstract: An integrated circuit (IC) device including a first memory device, a second memory device stacked with the first memory device, and one or more memory controllers configured to detect a first error in data stored in the first memory device at a first physical location in the IC device, and upon detecting the first error, determine whether there is a second error in data stored in the second memory device in a second physical location in the IC device near the first physical location.

Abstract: A system includes a MEMS sensor having dual proof masses capable of moving independently from one another in response to forces imposed upon the proof masses. Each proof mass includes an independent set of sense contacts configured to provide output signals corresponding to the physical displacement of the corresponding sense mass. A switch system is in communication with the sense contacts. The switch system is configured to enable a sense mode and various test modes for the MEMS sensor. When the switch system enables a sense mode, output signals from the sense contacts can be combined to produce sense signals. When the switch system enables a test mode, the second contacts are electrically decoupled from one another to disassociate the output signals from one another. The independent sense contacts and switch system enable the concurrent compensation and calibration of the proof masses along two different sense axes.

Abstract: A receiver circuit comprising a beamformer and an MRC-block. The beamformer configured to: apply combination-weighting-values to a first-BF-input-signal and a second-BF-input-signal in order to provide a BF-combination-signal; and apply suppression-weighting-values to the first-BF-input-signal and the second-BF-input-signal in order to provide a BF-suppression-signal. The MRC-block comprising: a first-demodulator configured to demodulate the BF-combination-signal in order to provide a demodulated-combination-signal that comprises bit metrics; a second-demodulator configured to demodulate the BF-suppression-signal in order to provide a demodulated-suppression-signal that comprises bit metrics; and a combiner configured to combine the demodulated-combination-signal with the demodulated-suppression-signal in order to provide an MRC-output-signal.

Abstract: An electromagnetic induction antenna including: a first inductor including windings; a second inductor including windings spaced apart from the first inductor; and an impedance connecting the first and second inductors; wherein the first and second inductor form a capacitor; wherein the capacitor is an electric field antenna, and wherein the inductor is a magnetic field antenna.

Abstract: A method of implementing a method of mapping an input message to an output message by a keyed cryptographic operation, wherein the keyed cryptographic operation includes a plurality of rounds using a Feistel network, including: receiving an input having a first half and a second half; performing, by a basic block, a portion of a round function on the second half to produce a portion of an encoded output, and wherein the basic block provides a portion of the second half as a portion of an encoded first input to a next round; and XORing the portion of the encoded output and a portion the first half to produce a portion of an encoded second input to the next round.

Abstract: A power converter, configured to convert AC mains power to a DC output voltage which is lower than the AC mains' peak voltage, is disclosed. It comprises: a capacitor configured to store charge at a voltage range which is intermediate the peak voltage and the DC output voltage; a gated rectification stage comprising a rectifier for rectifying an AC mains power, and at least one switch configured to supply the rectified AC mains power to the capacitor during only a low-voltage part of a half-cycle of the AC mains; and a switched mode DC-DC power conversion stage comprising at least one further switch and configured to convert power from the capacitor to the DC output voltage during only a high-voltage part of the half-cycle. A controller for use in such a converter, and a corresponding method, are also disclosed.

Abstract: One example discloses an apparatus for near-field magnetic induction (NFMI) based robustness, including: a first wireless device including a first wireless signal interface and a first NFMI signal interface; wherein the first wireless signal interface is configured to receive a data set from a third wireless device; wherein the first NFMI signal interface is configured to communicate with a second wireless device through a second NFMI signal interface; and wherein the first wireless device is configured to detect an error in the data set received from the third wireless device and in response to detecting the error configure the first NFMI signal interface to receive the data set from the second wireless device through the second NFMI signal interface.

Abstract: An integrated circuit device includes a first line in a first metal layer of the integrated circuit device, wherein the first line forms at least a portion of an interconnect, a second line in a second metal layer of the integrated circuit device, and a first via that couples the first line to the second line. The integrated circuit device further includes a first stressor disposed at a first area of the interconnect, wherein the first area at least partially overlaps the first via, wherein the first stressor alters an electromigration stress profile for the interconnect by altering a stress at the first area to be less tensile.

Abstract: An ESD protection circuit and device structure comprises five transistors, two PNP and three NPN. The five transistors are coupled together so that a first NPN and PNP pair constitute a first silicon controlled rectifier, SCR. The NPN transistor 102 of the first SCR and a third transistor of NPN type are coupled so that they constitute a Darlington pair. A further NPN and PNP pair are coupled together to form a second SCR with the collector of the PNP transistor of the first SCR being coupled with the emitter of the PNP transistor of the second SCR. The circuit is particularly suitable for high voltage triggering applications and two or more devices may be cascaded in series in order to further increase the triggering voltage.

Abstract: Disclosed is a method of charging a battery, including determining at a first time interval a current to be applied until a second time interval such that the current charges the battery so that an anode Li-ion surface concentration at the second time interval is kept smaller than or equal to a maximum Li-ion surface concentration of the anode, applying the current to the battery, and determining at the second time interval another current to be applied until a third time interval such that the another current charges the battery so that an anode Li-ion surface concentration at the third time interval is kept smaller than or equal to the maximum Li-ion surface concentration of the anode.

Abstract: Embodiments of a method and system are disclosed. One embodiment of a method for address decoding in a data communications system using a serial data transfer bus is disclosed. The method involves, detecting a start command from a master device of the data communications system at the serial data transfer bus, and disabling an address decoder of a slave device of the data communications system in response to the detecting the start command.

Abstract: An analog-to-digital converter including a converter arrangement configured to provide a digital output signal as an output of the analog-to-digital converter based on an analog input signal comprising an input to the analog-to-digital converter, the analog-to-digital converter including a calibration module configured to provide calibration signalling to set one or more of a gain of one or more components of the converter arrangement and an offset of one or more components of the converter arrangement, the calibration module further configured to provide, as an output, diagnostic information based on the calibration signalling for use in determining the occurrence of a fault in the analog-to-digital converter.

Abstract: A system for assigning addresses to a plurality of communication nodes coupled via a power line is disclosed. Each of the plurality of communication nodes includes a current sensor. The plurality of communication nodes includes one master communication node and the master communication node is configured to start an auto-addressing process by asking the each of the plurality of communication nodes to sink a preselect amount of current and measure current, through the current sensor, flowing through the powerline under the each of the plurality of communication nodes. A first communication node in the plurality of communication nodes that does not measure any current flowing under the first communication node is assigned a first address.

Abstract: A data processor is disclosed. The data processor includes a data processing module. The data processing modules includes an input for receiving an input signal, an output for providing a quantized output signal, a combining unit configured to combine a feedback signal from the output with the input signal and a quantizer configured to provide the quantized output signal based on the combined signal. The data processor further includes a correction module configured to receive the quantized output signal, generate a full-scale digital signal based on the quantized output signal, determine a metastability error in the full-scale digital signal and provide a compensated output signal based on the quantized output signal and the determined metastability error.