Abstract: An active thermal management device and method, in which a phase change material unit, comprising at least one phase change material arranged in series or parallel, is connectable to a source of thermal energy, such as LEDs at a first operating condition. Thermal energy from the source of thermal energy is stored in the phase change material unit. The phase change material unit is connectable to a sink of thermal energy, such as second LEDs at a second operating condition. The thermal energy stored in the phase change material unit may be re-used. The first operating condition can include a 15V supply voltage, and the second operating condition can include either no supply voltage, or a lower 9V supply voltage of 9V, such that heat from the first LEDs, which may be over-temperature, can pre-heat the second LEDs, improving thermal and optical matching.

Abstract: This disclosure describes a design tool that iteratively performs simulation sets on an integrated circuit design, each corresponding to a different hierarchical level with each of the simulation sets producing a different set of simulation results. Each of the simulation sets utilizes a different set of local parameter values that include extreme instance local parameter values based on the set of simulation results of a preceding simulation set. The design tool generates a set of hierarchically aggregated simulation results based upon the last set of simulation results and global parameters, and modifies the integrated circuit design based upon a yield estimation that is determined from comparing the set of hierarchically aggregated simulation results to specification requirements that correspond to the integrated circuit design.

Abstract: A data processing system includes a plurality of processing unit. Each processing unit includes notification storage circuitry configured to store a notification indicator corresponding to each processing unit which indicates whether the processing unit has an outstanding coherent memory request, and multiple request storage circuitry configured to store a multiple request indicator corresponding to each processing unit which indicates whether the processing unit has more than one outstanding request. The data processing system also includes an interconnect network coupled between the processing units and configured to broadcast coherent memory requests from a requesting processing unit of the plurality of processing units to other processing units of the plurality of processing units.

Abstract: A memory controller includes a transaction interface arranged to be coupled to a transaction interconnect to receive a write transaction comprising write data, a mode controller arranged to obtain context information and to select a data protection scheme out of a plurality of data protection schemes based on the obtained context information, at least one data protection module to apply the selected data protection scheme by generating one or more protection code sequences from at least the write data in accordance with the selected data protection scheme, and a physical memory interface coupled to at least one memory device to store the write data and the one or more protection code sequences in the at least one memory device.

Abstract: A processing device includes a target processor instruction memory to store a plurality of target processor instructions that include a plurality of global memory access instructions. The processing device further includes a compiler to communicate with the target processor instruction memory, the compiler including: a global variable candidate detection module to identify a global memory access instruction within a set of code regions that use a set of global variable candidates to access a global memory, and a memory access optimization module to modify the global memory access instruction, wherein the modified global memory access instruction utilizes an unused base pointer register of a set of unused base pointer register candidates within the set of code regions, a global variable from the set of global variable candidates to be used as a base address, and an offset relative to the base address to access the global memory.

Abstract: A television receiver, comprising a television signal input, a tuner, a frame buffer, a control input, a pattern recognition unit, and an electronic program guide unit. In operation, the television signal input receives a television signal. The tuner generates consecutive frames of a selected television channel on the basis of the television signal and is connected to a screen so as to drive the screen to display the frames consecutively. The frame buffer buffers the frames. The control input receives a scheduling request triggered by a user. The pattern recognition unit determines one or more program schedule values in response to the scheduling request, by performing an automatic pattern recognition analysis of one or more frames residing in the frame buffer. The electronic program guide unit provides program schedule information and updates the program schedule.

Abstract: A gain calibration controller and gain calibration method is described for calibrating the gain of a class D audio amplifier comprising an adjustable gain stage and a feedback path coupled to an output of a reconstruction filter. The gain calibration controller detects a first output noise level in a first frequency range and a second output noise level in a second higher frequency range, varies the gain of the adjustable gain stage, determines a minimum stable gain value of a stable gain range from a change in at least one of the first and second output noise level in response to varying the gain of the adjustable gain stage, and determines a maximum stable gain value of the stable gain range from a change in at least one of the first and second output noise level in response to varying the gain of the adjustable gain stage.

Abstract: An integrated circuit receives test-control information that is phase encoded on a scan clock used for testing a scan chain within the IC. The phase encoding does not affect the normal use of the scan clock and scan test chain and allows additional test-related data such as power supply, clock, and additional global and specialized status data to be collected by a secondary test data storage system such as a shift register. The phase encoding further controls selectively outputting the enhanced test status or the traditional scan test outputs.

Abstract: A method includes determining a quality indicator designating a quality of packet reception at a wireless local area network transceiver. A Modulation and Coding Scheme (MCS) index value is selected based on the quality indicator. A supply voltage provided to a radio frequency power amplifier is determined based on the quality indicator.

Abstract: Embodiments of a controller integrated circuit (IC) device for a switched mode power converter and a method of operating a controller IC device of a switched mode power converter are described. In one embodiment, a controller IC device for a switched mode power converter an input/output unit connected to an input/output node of the controller IC device and a controller unit. The input/output unit is configured to receive an input current from the input/output node and output an output voltage through the input/output node in response to an input voltage received at the input/output unit. The controller unit is configured to control voltage regulation of the switched mode power converter in response to the input current received from the input/output unit and generate the input voltage for the input/output unit. Other embodiments are also described.

Abstract: A device for over-temperature detection having a test mode is presented. The device includes a temperature detection circuit having first and second transistors. The temperature detection circuit is configured so that when an ambient temperature of the temperature detection circuit is less than a temperature threshold, a voltage at an emitter terminal of the second transistor is less than a voltage at an emitter terminal of the first transistor minus VT*In(N), and when the ambient temperature of the temperature detection circuit is greater than the temperature threshold, the voltage at the emitter terminal of the second transistor is greater than a voltage at the emitter terminal of the first transistor minus VT*In(N). The device includes a measurement circuit configured to generate an output voltage that is proportional to a difference between the temperature threshold of the temperature detection circuit and the ambient temperature of the temperature detection circuit.

Abstract: A method of recovery from a time-synchronization loss in a communication unit between a first processor supporting physical layer communications and a second processor supporting layer-2 communications is described.

Abstract: Apparatus are provided for amplifier systems and related circuits are provided. An exemplary circuit includes a main amplifier arrangement, first impedance matching circuitry coupled between the output of the main amplifier arrangement and a first output of the circuit, a peaking amplifier arrangement, and second impedance matching circuitry coupled between the output of the peaking amplifier arrangement and a second output of the circuit. In one exemplary embodiment, the first impedance matching circuitry and the second impedance matching circuitry have different circuit topologies and different physical topologies.

Abstract: A low dropout regulator (LDO) system includes a first pseudo random binary sequence (PRBS) generator configured to output a first PRBS signal; an LDO configured to output an LDO output signal and having an error amplifier, wherein the first PRBS generator is coupled to an input of the error amplifier; a second PRBS generator configured to output a second PRBS signal; and a correlator coupled to the LDO and second PRBS generator and configured to correlate the LDO output signal with the second PRBS signal to provide an impulse response data sample of the LDO.

Abstract: A data administration unit for updating a first data structure in a first memory may comprise a second memory, a data structure generator for setting up a second data structure in the second memory, a pointer generator for setting at least one of a dynamic change indicator and a pointer in the first data structure, a waiting unit for waiting for a finalization of a data access of a data access unit, and a data structure over-writer for overwriting the first data structure using data of the second data structure. An data access unit for accessing a first data structure in a first memory may comprise a data access driver, a first synchronization signal evaluator for reception and evaluation of a first synchronization signal, and a synchronization approval signal generator for generation and submission of a first synchronization signal.

Abstract: Methods and systems are provided that use smartcards, such as subscriber identity module (SIM) cards to provide secure functions for a mobile client. One embodiment of the invention provides a mobile communication network system that includes a mobile network, a mobile terminal, a server coupled to the mobile terminal via the mobile network, and a subscriber identity module (SIM) card coupled to the mobile terminal. The SIM card includes a first key and a second key. The first key is used to authenticate an intended user of the mobile terminal to the mobile network. Upon successful authentication of the intended user to the mobile network, the mobile terminal downloads a function offered from the server through the mobile network. The second key is then used by the mobile terminal to authenticate the intended user to the downloaded function so that the intended user can utilize the function.

Abstract: The present disclosure provides circuit and method embodiments for calibrating a signal of an integrated circuit. A programmable resistive element is coupled in series with a node of the integrated circuit, where at least part of the integrated circuit is formed in at least one front end of line (FEOL) device level. The programmable resistive element is formed in at least one back end of line (BEOL) wiring level, and the programmable resistive element is in a non-volatile resistive state that is variable across a plurality of non-volatile resistive states in response to a program signal applied to the programmable resistive element.

Abstract: A method for design rule verification is provided. The method comprises: providing a design rule check (DRC) deck based on a design rule manual (DRM) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of DRM test cases; assigning names to each of the plurality of DRM test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named DRM test cases to verify the DRC deck.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a CAN device includes a security module connected between a CAN bus interface of a CAN transceiver and a microcontroller communications interface of the CAN transceiver and an operational mode controller connected between the security module and the CAN bus interface. The security module is configured to perform a security function on data traffic received from the CAN bus interface or from the microcontroller communications interface. The operational mode controller is configured to set an operational mode for the CAN transceiver such that a CAN Flexible Data-rate (FD) frame or a corresponding CAN frame is output from the CAN bus interface. An identifier of the CAN FD frame is the same as an identifier of the corresponding CAN frame.

Abstract: A memory circuit includes a plurality of bit-cells organized in a column. Each bit-cell of the plurality is coupled to first and second voltage supply terminals, and first and second bit-lines. A word-line is coupled to a bit-cell of the plurality and configured to receive a first voltage during a first write operation. A first voltage generation circuit is coupled to the first voltage supply terminal and is configured to provide a first reduced voltage during the first write operation. A second voltage generation circuit is coupled to the second voltage supply terminal and is configured to provide a second reduced voltage during the first write operation.