Abstract: A filter circuit comprising a first feedback circuit configured to: receive a sensed-voltage-level-signal representative of a sensed voltage across a current sensing element; receive a voltage-set-point-signal; and set a regulation-control-signal for a current regulation device such that the sensed-voltage-level-signal tends towards the voltage-set-point-signal. The filter circuit also comprises a second feedback circuit configured to: receive a predetermined-threshold-signal; and receive a regulation-control-voltage-signal, representative of a voltage level of the regulation-control-signal. The second feedback circuit is configured to adjust the voltage-set-point-signal in accordance with a comparison between the regulation-control-voltage-signal and the predetermined-threshold-signal.

Abstract: A mechanism is provided by which communication is reduced between a data plane of a network device and a control plane associated with that network device upon introduction of a new flow. A holding table is provided for every active flow table in the data plane. The holding table holds flow contexts for new flows not found in the associated active flow table, while awaiting flow information from the control plane. Each flow context includes a queue of subsequent data packets associated with the flow, which are held from the control plane pending receipt of the flow information from the control plane. A timeout mechanism compensates for packet loss between the network device and control plane. When the data plane receives the flow information from the control plane, the data plane then processes all the queued packets, deletes the flow context, and enters the data into an associated flow table.

Abstract: There is described a driver circuit (100) for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch (110) comprising a first latch input terminal (111), a first latch control terminal (112), a latch voltage supply terminal (113), a first latch output terminal (114), and a second latch output terminal (115), wherein the level shifter latch (110) is adapted to provide, in dependency of a voltage at the first latch input terminal (111), one of a first voltage and a second voltage at the first latch output terminal (114) and the other one of the first voltage and the second voltage at the second latch output terminal (115), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal (113) and the second voltage is dependent on a voltage applied to the first latch control terminal (112), (b) a first output stage (120) comprising a first switching element (N11, N12), a second switching element (N13), a first voltage supply t

Abstract: Embodiments of a circuit for use with a DC-DC converter are disclosed. In an embodiment, a circuit for controlling frequency variation for a ripple based, constant-on time DC-DC converter, is discloses. The circuit includes a set/reset (SR) latch, a comparator configured to set the SR latch, and an on-time and frequency variation controller configured to reset the SR latch. The on-time and frequency variation controller includes a feedback loop configured to increase the rate at which a ramp voltage increases to reduce the time it takes for the ramp voltage to exceed a threshold voltage. Embodiments of a method for controlling frequency variation for a ripple based, constant-on time DC-DC converter are also disclosed.

Abstract: A network node for a wireless network and corresponding methods for reducing collisions in a wireless network, a wireless network, a wireless sensor network and a smart building including a wireless sensor network. The network node includes a processor, memory and an antenna. The network node is operable in a promiscuous mode to: receive at least one acknowledgement, wherein each acknowledgement is an acknowledgement of a respective transmission sent by another node through the wireless network; determine, from the at least one acknowledgement, timing information relating to the timing of the respective transmission(s) sent by the other node; and use the timing information to schedule transmissions sent by the node to reduce the probability of collisions of with transmissions sent by the other node.

Abstract: An ignition control device having an Electronic Fuel Injection mode and a Capacitive Discharge ignition mode is described. The ignition control device comprises: an output for providing an output voltage, connected or connectable to a load, the load being a fuel injection actuator of an EFI system or an ignition capacitor of a CDI system; and a driver unit connected to the output, for driving the output voltage from a low level to a high level and from the high level to the low level in dependence on an input signal, each transition of the output voltage from the low level to the high level having a low-to-high transition time which is longer for the CDI mode than for the EFI mode.

Abstract: Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.

Abstract: A sensor package includes a magnetic field sensor and a corruption detection and reset subsystem. The magnetic field sensor has a magnetic sense element and a ferromagnetic structure characterized by a baseline magnetic state. The subsystem includes a detector element, a processor, and current carrying structure positioned in proximity to the ferromagnetic structure. Methodology performed by the subsystem entails detecting at the detector element an altered magnetic state of the ferromagnetic structure, where the altered magnetic state differs from the baseline magnetic state. Methodology further entails determining, at the processor, when a reset action is needed in response to the altered magnetic state and applying a reset magnetic field to the ferromagnetic structure to reset the ferromagnetic structure from the altered magnetic state to the baseline magnetic state.

Abstract: A ground-loss detection circuit for an integrated circuit, (IC) device including a first dynamic threshold metal oxide semiconductor (DTMOS) device operably coupled between a first ground plane of the IC device and at least one further ground plane of the IC device, at least one of the first and at least one further ground planes comprising an external ground connection of the IC device, at least one further DTMOS device operably coupled between the first and at least one further ground planes of the IC device in an opposing manner to the first DTMOS device, and at least one ground-loss detection component operably coupled to at least one of the first and at least one further DTMOS devices and arranged to detect a ground-loss for at least one of the first and at least one further ground planes based at least partly on a drain current of the at least one of the first and at least one further DTMOS device(s).

Abstract: A data processing device includes a hash table management module that sequentially steps through linear address space of the hash table to identify hash chain in sequential address order. Each identified hash chain is evaluated, before identifying a next hash chain, to remove any entries marked for deletion.

Abstract: A method and apparatus for handling incoming data frames within a network interface controller. The network interface controller comprises at least one controller component operably coupled to at least one memory element. The at least one controller component is arranged to identify a next available buffer pointer from a pool of buffer pointers stored within a first area of memory within the at least one memory element, receive an indication that a start of a data frame has been received via a network interface, and allocate the identified next available buffer pointer to the data frame.

Abstract: Embodiments of a method and a system for generating a received signal strength indicator (RSSI) value that corresponds to a radio frequency (RF) signal are disclosed. In an embodiment, a method for generating an RSSI value that corresponds to an RF signal involves obtaining an attenuation factor code in response to applying an automatic gain control (AGC) operation to the RF signal, obtaining an analog-to-digital converter (ADC) code in response to applying an ADC operation to a signal that results from the AGC operation, and combining the attenuation factor code and the ADC code to generate an RSSI value. Other embodiments are also described.

Abstract: Methods and system for carrier frequency offset (CFO) estimation are described. The method includes determining correlation values between a plurality of samples from a received signal and a plurality of reference signals corresponding to a plurality of CFO candidates. A set of correlation values which exceeds a threshold is determined and a corresponding CFO candidate for each correlation value in the set is selected. A CFO estimate based on an interpolation of selected CFO candidates is then calculated.

Abstract: In an embodiment, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an Ethernet frame processor, at least one Ethernet port coupled to the Ethernet frame processor, and a hardware synchronization circuit coupled to the Ethernet frame processor and to the at least one Ethernet port, the hardware synchronization circuit including a controller, a local clock, a media-independent peripheral coupled to the controller, and a media-dependent peripheral coupled to the media-independent peripheral, wherein power can be provided to the hardware synchronization circuit independent of the Ethernet frame processor.

Abstract: A method of controlling direct memory access of a peripheral memory of a peripheral by a master is described. The method includes checking whether there is a pending request from the peripheral for a direct memory access service, establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and, if the access condition is satisfied, granting access to the master. Also, an associated device and an associated computer program product are described.

Abstract: Various exemplary embodiments relate to a method performed by an RFID tag, the method including: receiving a request for a EPC serial number; determining whether the EPC serial number has a preset value; when the EPC serial number has the preset value, mapping a transponder ID to the EPC serial number; and providing the EPC serial number in response to the RFID read request.

Abstract: A first doped region extends from a top surface of a substrate to a first depth. An implant into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.

Abstract: A method of designing an integrated circuit is described. The integrated circuit comprises a plurality of circuit components, including one or more functional components and one or more tile shapes. A pcell instance may be defined to specify a functional component along with one or more tile shapes. The tile shapes are thus associated with the functional component. A netlist may be arranged to specify interconnections between the functional components of the integrated circuit as well as electrical interactions between the tile shapes and functional components. A computer program product for carrying out the method is also described.

Abstract: Aspects of the present disclosure are directed to methods, apparatuses and systems involving a switched probe contact. According to an example embodiment, an apparatus includes logic circuitry, a first circuit to communicate signals with the logic circuitry, and a first bond pad connected to the first circuit via a first circuit path. The apparatus also includes a second circuit to communicate signals with the logic circuitry, and a second bond pad connected to the second circuit via a second circuit path. A probe contact is connected to the first bond pad and communicates signals with an external probe, and a switch circuit is connected to the probe contact and the second circuit path. The switch circuit communicates signals between the probe contact and the second circuit path by selectively connecting and disconnecting the probe contact to the second circuit path.

Abstract: A voltage supply regulator includes a first output resistor including a first terminal coupled to an output voltage of the voltage supply regulator and a second terminal; a first comparator including a first input coupled to a reference voltage, a second input coupled to the second terminal of the first output resistor, and an output coupled to a base of a first regulator transistor; a current mirror coupled to a collector of the first regulator transistor; and an slew rate detector coupled to the current mirror that includes a first terminal coupled to control electrodes of first and second transistors in the current mirror, and a detection bipolar junction transistor having a collector coupled to the control electrodes of the first and second transistors in the current mirror, and a base coupled to a second terminal of the capacitor.