Abstract: A system for determining tread wear of a tire includes a first wireless communication chip located at an inner surface of the tire and a second wireless communication chip located at an outer surface of the tire. The second chip resides in a slot extending through a housing located in a groove in a tread of the tire. The second chip moves in the slot toward the bottom of the groove in response to the tread wear. Methodology entails transmitting a first signal from a first chip, receiving the first signal at the second chip, transmitting a second signal from the second chip in response to receipt of the first signal, receiving the second signal at the first chip, computing a time delay between transmission of the first signal and receipt of the second signal, and determining tread wear of the tire in response to the time delay.

Abstract: A digital device comprising a functional unit, a real-time performance information unit, and a monitoring unit is described. The real-time performance information unit provides real-time performance information about the functional unit. The real-time performance information unit enables the local host device to retrieve the real-time performance information from the real-time performance information unit. The monitoring unit retrieves the real-time performance information from the real-time performance information unit. The monitoring unit has a network interface for connecting to a network. The monitoring unit is arranged to upload the real-time performance information to the network via the network interface. A method of operating the digital device is also described.

Abstract: A semiconductor device includes a semiconductor substrate, a body region disposed in the semiconductor substrate and having a first conductivity type, a composite source region disposed in the semiconductor substrate adjacent the body region and having a second conductivity type, and a gate structure supported by the semiconductor substrate and having a side adjacent the composite source region. The composite source region includes a plurality of first constituent source regions disposed along the side of the gate structure and having the second conductivity type, and a second constituent source region disposed along the side of the gate structure and between two first constituent source regions of the plurality of first constituent source regions, the second constituent source region having the second conductivity type. The second constituent source region has a different dopant concentration level than the plurality of first constituent source regions.

Abstract: A built-in self test system comprises an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry; a low power control unit operable to switch the integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering the low power mode; and a built-in self test control unit coupled to the built-in self test circuitry and the low power control unit and arranged to initiate a built-in self test when receiving the BIST wake-up signal.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a Controller Area Network (CAN) device includes a security module connected between a CAN bus interface of a CAN transceiver and a microcontroller communications interface of the CAN transceiver and a shield device connected between the CAN bus interface and the microcontroller communications interface. The security module is configured to perform a security function on data traffic received from the CAN bus interface or from a Serial Peripheral Interface (SPI) interface of the microcontroller communications interface. The shield device is configured to direct CAN Flexible Data-rate (FD) traffic received from the CAN bus interface to the security module.

Abstract: A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.

Abstract: The present disclosure relates in general to devices, systems and methods for wireless communication, and in particular to communication using a proximity integrated circuit card (PICC). Example embodiments include a circuit (100) for a PICC, the circuit comprising an input stage (101), a decoding module (106) and a bias adjustment module (117), the bias adjustment module (117) configured to receive an output code from the decoding module and provide a bias adjustment signal to the input stage (101), the bias adjustment module (117) configured to iteratively tune the bias adjustment signal based on a measurement of the output code, with successive steps tuning the bias adjustment signal by a smaller amount until the output code is within a decoding range.

Abstract: A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the drain region. The depletion region reaches a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. The depletion region establishes an electrical link between the buried doped isolation layer and the drain region such that the buried doped isolation layer is biased at a voltage level lower than the voltage applied to the drain region.

Abstract: A method for detecting a freeze-frame condition comprises receiving a sequence of images from at least one digital device; selectively encoding a first subset of the sequence of images using a first coding scheme that causes an adjustment to an image characteristic of the selected images being encoded; selectively encoding a second subset of the sequence of images using a second coding scheme; storing the first encoded subset and second encoded subset; retrieving the stored first encoded subset and second encoded subset; selectively decoding the first subset of the selected images using the first coding scheme and selectively decoding the second subset of the selected images using the second coding scheme to re-create the sequence of images. A freeze-frame condition in the re-created sequence of images is identifiable based on a plurality of decoded images being different with respect to the image characteristic across multiple decoded image frames.

Abstract: In a memory having a memory array, a method includes reading read data from the memory array, and detecting a first bit error in the read data. The method further includes checking all bitcells in a radial search region about the first bit error. The radial search region is defined by a search radius which indicates a number of concentric rings of bitcells physically surrounding the first bit error in the memory array.

Abstract: An electronic fault detection unit is provided that has a first register, a second register, a comparator circuit, and a timer circuit. The first and second register can be written from a first software portion, and a second software portion, respectively. The comparator circuit is arranged to detect that both the first and second register have been written, verify a relationship between first data written to the first register and second data written to the second register, and signal a fault upon said verification failing. The timer circuit is arranged to signal a fault if said verification of the comparator circuit does not occur within a time limit.

Abstract: Various aspects are directed to apparatuses, systems and related methods involving the mitigation of issues relating to thermal expansion and contraction of lead fingers of an integrated circuit package. Consistent with one or more embodiments, lead fingers on a leadframe substrate each have a locking structure that secures the lead finger in place relative to the substrate. The lead fingers provide a location to attach a bond wire to an integrated circuit, and connect the bond wire to terminals at a perimeter of the leadframe. The locking structure and arrangement of the lead fingers mitigate issues such as cracking or breaking of a solder connection of the bond wire to the leadframe, which can occur due to thermal expansion and contraction.

Abstract: Some embodiments include a resistor that may be used in audio conversion for an ADC. The resistor may be made up of an n-well as well as a p-well polysilicons. The n-well and p-well polysilicons may include a shallow trench isolator. The n-well and p-well components may be in series with other n-well or p-well components respectively. Similarly, multiple n-well components which are in series, may be in parallel with multiple p-well components.

Abstract: A packaged RF device is provided that utilizes flexible circuit leads. The RF device includes at least one integrated circuit (IC) die configured to implement the RF device. The IC die is contained inside a package. In accordance with the embodiments described herein, a flexible circuit is implemented as a lead. Specifically, the flexible circuit lead is coupled to the at least one IC die inside the package and extends to outside the package, the flexible circuit lead thus providing an electrical connection to the at least one IC die inside the package.

Abstract: A method of estimating a fragment count for the display of at least one three-dimensional (3D) object. The method comprises determining an ellipsoid representative of a set of vertices defined by coordinates of the at least one 3D object, applying a transformation to the ellipsoid, calculating a projection area of the transformed ellipsoid, and estimating the fragment count for the display of the 3D object based at least partly on the calculated projection area of the transformed ellipsoid.

Abstract: A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.

Abstract: The present disclosure provides embodiments for methods and memory devices. One embodiment of a memory device includes a first volatile memory cell having a first volatile access transistor with a current electrode coupled with a first volatile bit line; a first non-volatile memory cell having a first non-volatile access transistor with a current electrode coupled with a first non-volatile bit line; and a transfer circuit coupled between the first volatile bit line and the first non-volatile bit line. The transfer circuit is configured to: couple data latched from the first volatile bit line with the first non-volatile bit line during a store operation, and couple the first volatile bit line with the first non-volatile bit line during a restore operation.

Abstract: Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs having Embedded Ground Plane (EGP) connections are provided. In one embodiment, the method includes forming a molded panel around an EGP array from which a plurality of preformed EGP connections project. One or more Redistribution Layers (RDLs) are produced over the molded panel. The molded panel is then singulated to yield a plurality of FO-WLPs each including a molded package body containing an EGP from the EGP array and one or more of preformed EGP connections.

Abstract: A portion of a reprogrammable storage device is used to implement permanent data storage. The storage device includes a plurality of electrically erasable memory elements and a controller. The plurality of electrically erasable memory elements are configured to store data. Each memory element is programmable a number of write cycles before reaching a write failure state. The controller is coupled to the plurality of memory elements. The controller includes a receiver and a write engine. The receiver receives an instruction to drive a selected memory element to the write failure state. The write engine repeatedly writes a data value, in a plurality of write operations, to the selected memory element until the write failure state of the selected memory element is established.

Abstract: A system for programming integrated circuit (IC) dies formed on a wafer includes a magnetic field transmitter that outputs a digital test program as a magnetic signal. At least one digital magnetic sensor (e.g., Hall effect sensor) is formed with the IC dies on the wafer. The digital magnetic sensor detects and receives the magnetic signal. A processor formed on the wafer converts the magnetic signal to the digital test program and the digital test program is stored in memory on the wafer in association with one of the IC dies. The magnetic field transmitter does not physically contact the dies, but can flood an entire surface of the wafer with the magnetic signal so that all of the IC dies are concurrently programmed with the digital test program.