Abstract: The present disclosure provides for methods, network devices, and computer readable storage media for packet reordering. In one embodiment, a method includes receiving a first packet of a first flow at a network device and determining whether flow-identifying information extracted from the first packet matches an existing flow entry. The method also includes, in response to a determination that the flow-identifying information does not match any existing flow entries, generating a new transient flow entry that includes the flow-identifying information and packet-in state. The method also includes forwarding the first packet to a controller via a packet-in stream.

Abstract: A UHF-RFID antenna having a central segmented loop surrounded by passive dipole structures provides shaping of the electric and magnetic fields to reduce the number of false positive reads by a UHF-RFID reader at a point of sale.

Abstract: An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.

Abstract: A sensor device includes a substrate having a port extending through it and a membrane including a first electrode spanning across the port. The port exposes the membrane to a pressure stimulus from an external environment. A second electrode is spaced apart from the first electrode by a gap having a first width. A control circuit applies an actuation voltage to move the second electrode closer to the first electrode and change the gap to a second width that is less than the first width. When the gap is set to the second width, the pressure sensor exhibits a greater sensitivity then when the gap is set to the first width. The membrane with the first electrode is movable in response to the pressure stimulus and the pressure stimulus is sensed as movement of the first electrode relative to the second electrode while the actuation voltage is applied.

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.

Abstract: A memory device includes a sense amplifier coupled to a first read voltage during a first phase of a read operation and a second read voltage during a second phase of the read operation. A first and second bias voltages are based on the first and second read voltages and corresponding current on a bit line. A first capacitor includes a terminal coupled to the first and second bias voltages. A first amplifier includes an input coupled to another terminal of the first capacitor and another input coupled to a common mode voltage during the first phase and to a reference voltage during the second phase. A second capacitor includes a terminal coupled to an output of the first amplifier. A second amplifier includes an inverting input coupled to another terminal of the second capacitor and another input coupled to a common mode voltage.

Abstract: Aspects of the present disclosure are directed to methods, apparatuses and systems involving voltage control using rectifying circuitry. According to an example embodiment, an apparatus includes an antenna, a capacitor, and voltage control circuitry. The voltage control circuitry includes a first rectifying circuit to rectify a wireless signal and provide the rectified signal to an output load, a second rectifying circuit to rectify the wireless signal and provide the rectified signal to the capacitor, and a control logic circuit to regulate an output voltage provided to the output load relative to a threshold value. For each rectifying cycle, the control logic circuit determines whether the output voltage is above the threshold value, enables, in response to determining that the output voltage is below the threshold value, the first rectifying circuit, and enables, in response to determining that the output voltage is above the threshold value, the second rectifying circuit.

Abstract: The present invention relates to the implementation for implementing multi-tasking on a digital signal processor. For that purpose blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. While the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.

Abstract: The invention relates to a method of designing a processor core arrangement which comprises a first processor core for operation at a first operation frequency and having an associated first leakage and a second processor core for operation at a second operation frequency lower than the first operation frequency and having an associated second leakage lower than the associated first leakage. The processor core arrangement is capable of switching from the first processor core to the second processor core and vice versa.

Abstract: A method of accessing, in a mobile communication device, an application issued by a Service Provider from a trusted application, also known as a wallet. A secure element, such as a SmartMX device, comprises a service manager that manages the application and a link between the application and an application-codec issued by the Service Provider, wherein the application-codec is designed for interfacing between the service manager and the application, for processing an access request requesting access to the application received from the service manager and, triggered by the wallet, accessing the application via the service manager by means of the link between the application and the application-codec, such that the application-codec linked with the respective application performs accessing the application under control of the service manager.

Abstract: A data processing device provided with an error detection unit includes a processor arranged to support execution of an operation including a first sequence of instructions and execution of a second sequence of instructions implementing the operation, the first and second sequences of instructions generating, when in use, a first result and a second result, respectively. Configurable circuitry is also provided and arranged to support a repository to receive the first result and the second result following generation thereof. The configurable circuitry is configured as a function comparator unit arranged to compare the first and second results for consistency and to control further execution of the first implementation and the second implementation in response to a result of the comparison.

Abstract: A method, apparatus, and energy metering system obtains mains samples of a mains power line signal, performs non-white noise (NWN) filtering of the mains power line signal, obtains adjustable clock source samples of an adjustable clock signal of an adjustable clock oscillator, determines a difference based on the mains samples and the adjustable clock source samples, adjusts an adjustable clock source frequency of the adjustable clock oscillator based on the difference, and applies the adjustable clock source frequency to an analog to digital converter (ADC) to determine a conversion rate of the ADC.

Abstract: The embodiments described herein provide a power transmitter for wireless charging of an electronic device and methods of its operation. The power transmitter uses an inverter configured to generate a square wave from a potentially wide ranging DC input voltage. The inverter is configured to generate the square wave with a duty cycle that results in a desired equivalent voltage output, effectively independent of the DC input voltage that is provided. Thus, by generating a square wave with a selectable duty cycle the inverter provides the ability to facilitate wireless power transfer with a wide range of DC input voltages. Furthermore, in some embodiments the power transmitter may provide improved power transfer efficiency using a quasi-resonant phase shift control strategy with adjustable dead time and a matching network that is dynamically selectable to more effectively couple with the transmitter coil combination being used to transmit power to the electronic device.

Abstract: An integrated circuit for bias stress condition removal comprising at least one input/output (IO) buffer driver circuit comprising at least one input signal is described. A primary buffer driver stage receives the at least one input signal and providing an output signal in a first time period; and a secondary buffer driver stage receives the at least one input signal and providing an output signal in a second time period. The primary buffer driver stage and the secondary buffer driver stage cooperate and an operational mode of the primary buffer driver stage and an operational mode of the secondary buffer driver stage is varied to produce a varying output signal.

Abstract: A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements, each comprising a pinned layer having a reference magnetization parallel to a plane of the sensor and a sense layer having a sense magnetization. A permanent magnet layer spaced apart from the sense elements magnetically biases the sense magnetization into an out-of-plane direction that is non-perpendicular to the plane of the sensor. The sense magnetization of a portion of the sense elements is oriented in a first direction and the sense magnetization of a different portion of the sense elements is oriented in a second direction differing from the first direction to generate two unique bias field vectors of the sense layers which enables detection of the external magnetic field in a sensing direction that is perpendicular to the plane of the magnetic field sensor without inter-axis coupling of sensor response.

Abstract: A voltage regulator for digital loads combines a closed loop regulation circuit with an open loop topology. A transistor and a bank of transistors share the same voltage source VDD and gate control current. Each of the bank of transistors is sized to match different current load requirements and one or more may be switched in or out as appropriate when the digital load transitions from one operating mode to another. The regulator has good DC load regulation and unconditional stability regardless of output capacitance.

Abstract: An apparatus including: an input interface configured to enable user configuration of a future time window; and a report interface configured to produce a report relating to a first sub-set of a plurality of active timers that expire at programmed future points in time, wherein the first sub-set of the plurality of active timers expire during the user-configured future time window.

Abstract: A reset state control circuit adapted to reset independent device domains of an electronic device, said reset state control circuit comprising a capturing unit adapted to capture reset events; and a reset shaping logic adapted to change dynamically a reset control flow to reset device domains of said electronic device depending on a sequence of the reset events captured by said capturing unit.

Abstract: A frequency divider circuit can achieve multi-modulus operation. The frequency divider includes clocking transistor devices, memory transistor circuits, write transistor devices, and a current source bias. The clocking transistor devices receive a differential input signal having a first frequency at an input of the frequency divider. The memory transistor circuits store signals based on the differential input signal from the clocking transistor devices. The write transistor devices make a divided frequency signal available at an output terminal. The current source bias is coupled to the clocking transistor devices. The current source bias applies a bias current to adapt the frequency divider to a common-mode at the input of the frequency divider.

Abstract: A method is provided of performing register allocation for at least one program code module. The method includes constructing a restriction graph for program variables within at least one program instruction, and determining whether the constructed restriction graph is colorable. If it is determined that the constructed restriction graph is not colorable, then the method determines whether at least one alternative form of the at least one program instruction is available, and modifies the at least one program instruction to comprise an alternative form if it is determined that at least one alternative form is available.