Abstract: Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.

Abstract: An approach is provided in which an endianness violation detection sub-system detects endianness violations between hardware units. The endianness violation detection sub-system tracks memory operations performed by multiple hardware units via debug channels and generates lookup table entries that are stored in a lookup table. When the endianness violation detection sub-system detects endianness relevant load attributes of a load operation that are different than corresponding endianness relevant store attributes of a store operation, the endianness violation detection sub-system generates an endianness violation. In one embodiment, the endianness violation detection sub-system identifies an endianness violation when the endianness violation detection sub-system detects a difference in the byte ordering type between a hardware unit performing a store operation and a hardware unit performing a load operation.

Abstract: A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.

Abstract: Techniques are provided for entering a secret into a security token using an embedded tactile sensing user interface with the purpose of verifying the secret against a stored representation of the same secret. In particular, an embodiment of the security token according to the invention comprises a tactile sensing user interface being arranged to receive a user-encoded secret, a decoding unit being arranged to generate a decoded secret by decoding the user-encoded secret, a comparison unit being arranged to compare the decoded secret with a copy of the secret stored in the token in order to verify the authenticity of a user. Thereby, the security token provides on-card matching functionality.

Abstract: An optimized hardware architecture and method introducing a simple arithmetic processor that allows efficient implementation of an Elliptic Curve Cryptography point addition algorithm for mixed Affine-Jacobian coordinates. The optimized architecture additionally reduces the required storage for intermediate values.

Abstract: Systems, methods, and circuits for determining one or more switch statuses are disclosed herein. In one example embodiment, such a system for determining a status of a switch having first and second terminals includes a first port configured to be coupled to the first terminal, a second port configured to be coupled to the second terminal, and a capacitor coupled between the first port and ground. Additionally, the system includes a comparator device having first and second input ports and an output port, the first input port being coupled at least indirectly to the first port, a current source coupled to the first input port, and a voltage source coupled between the second port and the second input port. The comparator device is configured to provide an output signal at the output port that is at least sometimes indicative of the status of the switch.

Abstract: A packaged device includes an extended structure located at a major side of the packaged device. The extended structure defines an outer area that includes encapsulated material on the major side and an inner area where there is a lack of encapsulant over a portion of the device at the major side. The extended structure prevents encapsulant from getting into the inner area during the encapsulating process.

Abstract: A method of testing a semiconductor device against electrostatic discharge includes operating the semiconductor device, and, while operating the semiconductor device, monitoring a functional performance of the semiconductor device. The monitoring includes monitoring one or more signal waveforms of respective one or more signals on respective one or more pins of the semiconductor device to obtain one or more monitor waveforms, and monitoring one or more register values of one or more registers of the semiconductor device to obtain one or more monitor register values as function of time. The method includes applying an electrostatic discharge event to the semiconductor device while monitoring the functional performance of the semiconductor device. The method can further comprise determining a functional change from the one or more monitor waveforms and the one or more monitor register values as function of time.

Abstract: A sensor circuit incorporates an analog to digital converter for providing a digital signal derived from sensing elements connected in a bridge configuration. The sensor circuit comprises first and second paths comprising respective first and second sensing elements connected between first and second supply lines; an analog to digital converter having a differential input connected to receive a differential voltage signal (Vinp?Vinn) between the first and second sensing elements and an output for providing a digital output signal (Dout) representing a difference between the first and second sensing elements, the analog to digital converter comprising: current sources connected between the first and second supply lines, each current source being switchably connected to either the first or second sensing elements; and control logic configured to selectively switch current from each of the current sources to either the first path or the second path in dependence on the differential voltage signal.

Abstract: A communication unit receiver comprising: a multi-section analog to digital converter, ADC, configured to receive an analog signal and convert at least a first portion of the analog signal into a digital signal using a first ADC dynamic range. A modem, coupled to the multi-section ADC, is configured to: process the digital signal; determine a signal-to-noise ratio, SNR, for sub-carriers of the analog signal; and output an ADC selection signal to the multi-section ADC that selects a subset of sections of the multi-section ADC, where the selection signal is based at least partly on the determined SNR. Only the subset of sections of the multi-section analog to digital converter, ADC is configured to convert a second portion of the analog signal into a digital signal using a second ADC dynamic range that is less than the first dynamic range.

Abstract: A system and methods controlling wake events in a data processing system is described. A broadcast wake-up signal staggering order is determined in response to a first wake event. A staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the broadcast wake-up signal staggering order. The broadcast wake-up signal staggering order is changed in response to a second wake event. And a changed staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the changed broadcast wake-up signal staggering order.

Abstract: An LED controller includes: a light intensity calculator to calculate light intensity values that correspond to points on a desired light output curve; and processing logic configured to: initialize a scaling parameter of the light intensity calculator with a present scaling value that indicates a first number of steps, dynamically receive a subsequent scaling value that indicates a second number of steps at a change time after the light intensity calculator has begun calculation of the light intensity values according to the present scaling value, and change the scaling parameter of the light intensity calculator to the subsequent scaling value before the light intensity calculator has completed calculation of the light intensity values, wherein a difference between a next light intensity value calculated immediately after the change time and a previous light intensity value calculated immediately before the change time is within a flicker threshold.

Abstract: An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.

Abstract: Semiconductor devices with cross-domain electrostatic discharge (ESD) protection and related fabrication methods are provided. An exemplary semiconductor device includes first domain circuitry, second domain circuitry, and an interface coupled between an output node of the first domain driver circuitry and second domain receiver circuitry. The receiver circuitry includes a transistor having a gate electrode coupled to the interface, with a body electrode of the transistor being coupled to protection circuitry of the first domain circuitry. The body electrode is effectively biased to a reference voltage node of the first domain by the protection circuitry in response to an ESD event to protect the gate oxide of the transistor from a potentially damaging ESD voltage.

Abstract: Embodiments of a buffer device, an electronic system, and a method for operating a buffer device are disclosed. In an embodiment, a buffer device includes buffer bus connections, a peripheral bus interface connectable to a peripheral bus, a buffer memory module, and a buffer memory controller connected between the buffer bus connections, the peripheral bus interface, and the buffer memory module. Each of the buffer bus connections is connectable to a respective peripheral device. The buffer memory module comprises memory segments corresponding to the peripheral devices. The buffer memory controller is configured to control data communications between the buffer bus connections, the peripheral bus interface, and the buffer memory module.

Abstract: Methods for fabricating microelectronic packages and microelectronic packages having split gyroscope structures are provided. In one embodiment, the microelectronic package includes a first Microelectromechanical Systems (MEMS) die having a first MEMS gyroscope structure thereon. The microelectronic package further includes a second MEMS die, which has a second MEMS gyroscope structure thereon and which is positioned in a stacked relationship with the first MEMS die. The first and second MEMS gyroscope structures overlap as taken along a first axis orthogonal to a principal axis of the first MEMS die.

Abstract: A system and method of mapping of a processing task to a target processor is provided. Kernels associated with unit of processing defined for a processor to operate on a processing operation on the target processor required to performing the processing task. A directed acyclic graph (DAG) comprising the kernels and specifying connections between the one or more kernels represents the desired processing task to be executed by the target processor is resolved from the kernels defined in the DAG to a process executed by a processor architecture of the target processor. Data sequencing is determined from the DAG for memory usage in executing the process. Host code is generated to configure and execute the process in relation to the kernel execution for the process resolved for the processing task.

Abstract: Mobile devices such as mobile phones typically have two speakers, one for use in a hand-set mode and one for use in a hands-free mode. A mobile device (1100) is described operable to switch between a hand-set mode and a hands-free mode, the mobile device includes a receiver speaker (10) operable in the hand-set mode and the hands-free mode of the mobile device, and a hands-free speaker (12) operable in the hands-free mode of the mobile device. The mobile device is operable in hands-free mode to route at least one audio signal to the receiver speaker and the hands-free speaker. Using the hands-free speaker and the receiver speaker may improve the sound quality without increasing the cost.

Abstract: A fault analysis method comprises: receiving fault data from wafer level testing that identifies locations and test results of a plurality of die; applying a kernel transform to the fault data to produce cluster data, where the kernel transform defines a fault impact distribution that defines fault contribution from the failed die to local die within an outer radial boundary of the fault impact distribution. Applying the kernel transform comprises: centering the fault impact distribution at a location of each die that failed wafer level testing, associating each local die that falls within the outer radial boundary with a respective fault contribution value according to the fault impact distribution, and accruing fault contribution values associated with each respective die of the plurality of die to produce a cluster value for the respective die, which correlates to a probability of failure of the respective die at a future time.

Abstract: A method of fabricating a bipolar transistor device includes performing a first plurality of implantation procedures to implant dopant of a first conductivity type to form emitter and collector regions laterally spaced from one another in a semiconductor substrate, and performing a second plurality of implantation procedures to implant dopant of a second conductivity type in the semiconductor substrate to form a composite base region. The composite base region includes a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions.