Abstract: A phase locked loop, comprising: a phase detector configured to determine a phase difference (??) between a reference signal and a feedback signal; a loop filter configured to perform a filtering operation on a signal derived from the phase difference, and to provide a control signal; a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal; wherein a low-pass filter is provided between the phase detector and the loop filter and/or between the loop filter and the frequency controlled oscillator to reduce quantization noise from the phase detector.

Abstract: An ESD protection structure comprising a thyristor structure. The thyristor structure is formed from a first P-doped section comprising a first P-doped well formed within a first region of a P-doped epitaxial layer, a first N-doped section comprising a deep N-well structure, a second P-doped section comprising a second P-doped well formed within a second region of the epitaxial layer, and a second N-doped section comprising an N-doped contact region formed within a surface of the second P-doped well. The ESD protection structure further comprises a P-doped region formed on an upper surface of the deep N-well structure and forming a part of the second P-doped section of the thyristor structure.

Abstract: Communications apparatus has a short range wireless radio frequency communicator (1301a) capable of at least one of seeking to initiate short range communication by transmitting an RF signal and of responding to such initiation so that communication between two short range wireless radio frequency communicators occurs when an antenna of a short range wireless radio frequency communicator seeking to initiate communication by transmitting an RF signal is in range of or comes into range of the antenna of another short range wireless radio frequency communicator responsive to such initiation so that the magnetic field of the RF signal transmitted by the short range wireless radio frequency communicator seeking to initiate communication is inductively coupled to the antenna of the short range wireless radio frequency communicator responsive to such initiation to enable communication of at least one of power and data between the short range wireless radio frequency communicators.

Abstract: A low drop-out voltage regulator (LDO) includes an LDO unit, a switch circuit, a charge pump, and an initiation circuit. The switch circuit is coupled to a voltage input terminal and outputs a selected input voltage. The LDO unit receives the selected input voltage from the switch circuit and generates a regulated output voltage. The charge pump is coupled to the LDO unit to receive the regulated output voltage, and generate a control signal that is provided to the switch circuit. The initiation circuit receives the input voltage and generates an initiation voltage that greater than the regulated output voltage. The initiation voltage is provided to the charge pump circuit, along with the regulated output voltage. The initiation voltage drives the charge pump circuit when the regulated output voltage is not large enough to drive the charge pump circuit.

Abstract: One example discloses a breach sensor, comprising: a substrate including an integrated circuit; a passivation layer coupled to the substrate; a breach sensing element coupled to the circuit; wherein the breach sensing element is on a first side of the passivation layer and the substrate is on a second side of the passivation layer; a barrier configured to separate the breach sensing element from an ambient environment; wherein the breach sensing element is responsive to barrier damage.

Abstract: An audio and ultrasound signal processing circuit (412), comprising: an audio input terminal (414) for receiving an input signal comprising an audio input signal; an amplitude detector (430), configured to determine an amplitude of the input signal and provide an amplitude level signal (432); a gain calculator (434) configured to determine an ultrasound amplification factor (436) in accordance with the amplitude level signal (432) and a target amplitude signal (418); a variable ultrasound amplifier (438) configured to receive an ultrasound input signal and modulate an amplitude of the ultrasound input signal in accordance with the ultrasound amplification factor (436) in order to provide an amplified ultrasound signal; and an output terminal (416) for providing an enhanced output signal comprising frequency components that correspond to the audio input signal and frequency components that correspond to the amplified ultrasound signal.

Abstract: A frequency shift keying (FSK) demodulation component having of a sampler that receives an FSK modulated signal, samples the received FSK modulated signal, and outputs the sampled signal. The FSK demodulation component further includes a low pass filter that filters the sampled signal, and a frequency shift detector that detects shifts in frequency of the low pass filtered sampled signal. The FSK demodulation component then outputs an indication of the detection of shifts in frequency of the low pass filtered sampled signal.

Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.

Abstract: A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.

Abstract: A FIR filter includes segment cells, each of which is configurable as an interpolation filter, a decimation filter, a symmetric filter, or an asymmetric filter. Two or more of the segment cells are configurable to be cascaded to form an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, or a complex asymmetric filter. The FIR filter includes registers corresponding to the segment cells for storing coefficient values of the corresponding segment cells. The FIR filter further includes control circuits corresponding to the segment cells for generating control signals.

Abstract: An integrated circuit (IC) having a clock switch that switches the system clock between an internal clock and an external clock based on whether or not the IC has finished downloading device configuration at boot and on whether or not the internal clock is functional. Further restrictions on the use of the external clock are imposed by the clock switch based on a life-cycle state of the IC. The use of the clock switch makes it significantly more difficult for the clock to be tampered with, thereby protecting the security settings of the IC and/or preventing unauthorized access to secure data stored on the IC using an external-clock-based security attack.

Abstract: A method of designing a layout of a metallization stack of an integrated circuit (IC), where the stack includes metal layers having patterned metal features. The method includes determining a layout of a first grid of the metallization stack, including patterned metal features for supplying power and providing signal connections to components of the IC. The method also includes determining a layout of a second grid of the stack for securing the IC against electromagnetic attacks. The second grid includes patterned metal features interspersed with the patterned metal features of the first grid in at least some of the metal layers of the metallization stack. The patterned metal features of the second grid are electrically connected to the first grid. The method further includes determining at least one layout change for the metallization stack in accordance with an engineering change order.

Abstract: A semiconductor sensor device is assembled using a lead frame having a flag surrounded by lead fingers. A pressure sensor die is mounted on the flag and electrically connected to the leads. Prior to encapsulation, a pre-formed block of gel material is placed over the sensor region on the die. Encapsulation is performed and mold compound covers the pressure sensor die and the bond wires. Mold compound covering the gel block may be removed. Additionally, a trench may be formed around an upper portion of the gel block so that the lateral sides of the gel block are at least partially exposed.

Abstract: A data processing system comprising at least a memory unit, a first client connected to the memory unit, and a second client connected to the memory unit is proposed. The first client may comprise a first memory access unit and an information unit. The first memory access unit may read data from or write data to the memory unit at a first data rate. The information unit may update internal data correlating with a minimum required value of the first data rate. The second client may comprise a second memory access unit and a data rate limiting unit. The second memory access unit may read data from or write data to the memory unit at a second data rate. The data rate limiting unit may limit the second data rate in dependence on the internal data. The first memory access unit may, for example, read data packets sequentially from the memory unit, and the information unit may update the internal data at least per data packet. A method of controlling access to a shared memory unit is also proposed.

Abstract: Switched mode power supply (SMPS) with adaptive reference voltage for controlling an output transistor and method of operating the SMPS are described. The adaptive reference voltage is implemented using a timer that starts when the voltage on a conduction terminal of the output transistor reaches a reference voltage and stops when the current through the output transistor reaches zero. The voltage difference between a target voltage and a voltage accumulated when the timer was active is then sampled to produce a sampled voltage, which defines a new reference voltage if the accumulated voltage is not equal to the target voltage so that the reference voltage is adaptively adjusted in accordance with an operational characteristic of the output transistor.

Abstract: An integrated circuit includes a normal voltage detector configured to detect a normal voltage at which the integrated circuit being fully functional. A first voltage detector detects a first voltage that is less than the normal voltage. A second voltage detector detects a second voltage that is less than the first voltage. A reset module is coupled to a supply voltage, the normal voltage detector, the first voltage detector, and the second voltage detector. The reset module includes test logic to, when the supply voltage rises to the first voltage from the second voltage, perform a pass/fail test when the integrated circuit is in a pass/fail test mode, and perform a power up reset when the integrated circuit in not in the pass/fail test mode.

Abstract: Embodiments are provided that include a light emitting diode (LED) controller connectable to a matrix of LEDs. A start code is received via at least one input pin, and a selected curve profile is retrieved from a programmable local memory in response to receipt of the start code, wherein the programmable local memory stores a set of curve profiles, each of which is associated with a different start code. A set of coefficients of a polynomial calculator are initialized to a set of values defined in the selected curve profile, wherein the set of values represent a light output curve. A sequence of light intensity values are calculated according to the polynomial calculator, and at least one pulse width modulation (PWM) signal is generated based on the sequence of light intensity values, wherein the at least one PWM signal controls light output of at least one LED.

Abstract: A semiconductor device includes a device die having a top surface, a bottom surface, and sidewalls between the top and bottom surfaces. A first protective layer covers at least the top surface and the sidewalls of the die. A thickness of the first protective layer on the sidewalls near the top surface is greater than a thickness of the first protective layer on the sidewalls die near the bottom surface.

Abstract: An apparatus, method and integrated circuit for broad-range current measurement using duty cycling are disclosed. Embodiments of an apparatus for sensing current through a transistor device may include an interface configured to receive a current from the transistor device for sensing. Additionally, embodiments may include a sensor component coupled to the interface and configured to receive the current from the transistor device and to generate a responsive sensor voltage. Embodiments may also include a sense control circuit configured to control a duty cycle of the sensor component.

Abstract: An apparatus for maintaining alertness of an driver of a motor vehicle periodically generates an audible alert signal to which the driver responds by pressing a button on the vehicle's steering wheel. The response time of the driver to the signal is monitored and if an increase is detected, the repetition rate of the alert signal is increased. The repetition rate may be further modified by taking into account vehicle driving conditions which may indicate a risk of boredom in the driver.