Patents Assigned to NXP
  • Loudspeaker controller
    Patent number: 9826294
    Abstract: A loudspeaker controller (1) for controlling a loudspeaker (2), configured to determine time-varying impedance information of the loudspeaker (2) based on a loudspeaker voltage and a measure of a loudspeaker current and provide for control of the loudspeaker (2) in accordance with said time-varying impedance information.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: November 21, 2017
    Assignee: NXP B.V.
    Inventors: Temujin Gautama, Alan OCinneide, Lutsen Ludgerus Albertus Hendrikus Dooper
  • Micro-electro-mechanical system drive-mode oscillator module and method therefor
    Patent number: 9823074
    Abstract: A drive-mode oscillator module for use within a micro-electro-mechanical system (MEMS) device is described. The drive-mode oscillator module is arranged to receive a proof-mass measurement signal from a proof-mass of the MEMS device and to output a proof-mass actuation signal to the proof-mass of the MEMS device. The drive-mode oscillator module comprises a first, higher gain accuracy drive-mode component for generating an actuation signal to be output by the drive-mode oscillator module during an active mode of the MEMS device, and a second, lower power consumption drive-mode component for generating an actuation signal to be output by the drive-mode oscillator module during a standby mode of the MEMS device.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: November 21, 2017
    Assignee: NXP USA, Inc.
    Inventors: Hugues Beaulaton, Laurent Cornibert, Gerhard Trauth
  • Programmable direct memory access channels
    Patent number: 9824242
    Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: November 21, 2017
    Assignee: NXP USA, INC.
    Inventors: Joseph C. Circello, Daniel M. McCarthy, John D. Mitchell, Peter J. Wilson, John J. Vaglica
  • Capacitive sensor device and method of operation
    Patent number: 9823798
    Abstract: A capacitive sensor system includes a capacitive sensor device having a sense electrode that includes a first capacitor, a first supply voltage in , a first switch operable to couple the sense electrode to the first supply voltage during a first mode and an analog to digital converter during a second mode, a second switch operable to couple a second capacitor to a second supply voltage during the first mode and to an open circuit during the second mode, and a resistive element that includes a first terminal coupled between the first capacitor and the first switch, and a second terminal coupled between the second capacitor and the second switch.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: November 21, 2017
    Assignee: NXP USA, Inc.
    Inventor: Petr Cholasta
  • Model-based runtime detection of insecure behavior for system on chip with security requirements
    Patent number: 9824243
    Abstract: A runtime classifier hardware circuit is incorporated into an electronic device for implementing hardware security by storing a support vector model in memory which is derived from pre-silicon verification data to define secure behavior for a first circuit on the electronic device; monitoring input and/or output signals associated with the first circuit using the runtime classifier hardware circuit which compares the input and/or output signals to the support vector model to detect an outlier input signal and/or outlier output signal for the first circuit; and blocking the outlier input and/or output signal from being input to or output from the first circuit.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: November 21, 2017
    Assignee: NXP USA, INC.
    Inventors: Wen Chen, Jayanta Bhadra, Lawrence L. Case
  • Microcontroller unit and method of operating a microcontroller unit
    Patent number: 9823959
    Abstract: A microcontroller unit having a functional state, a reset state, and one or more assertable fault sources is described. Each fault source has its own fault source assertion count and its own fault source assertion limit; the MCU is arranged to perform the following sequence of operations in a cyclic manner: if one or more of the fault sources are asserted, pass from the functional state to the reset state and increase the respective fault source assertion counts by one increment; if one or more of the fault source assertion counts exceeds the respective fault source assertion limit, disable the respective fault source; and pass from the reset state to the functional state. A method of operating an MCU is also disclosed.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: November 21, 2017
    Assignee: NXP USA, Inc.
    Inventors: Vladimir Litovtchenko, Joachim Fader, Harald Luepken
  • Vertical power transistor device, semiconductor die and method of manufacturing a vertical power transistor device
    Patent number: 9825162
    Abstract: A vertical power transistor device comprises: a substrate formed from a III-V semiconductor material and a multi-layer stack at least partially accommodated in the substrate. The multi-layer stack comprises: a semi-insulating layer disposed adjacent the substrate and a first layer formed from a first III-V semiconductor material and disposed adjacent the semi-insulating layer. The multi-layer stack also comprises a second layer formed from a second III-V semiconductor material disposed adjacent the first layer and a heterojunction is formed at an interface of the first and second layers.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: November 21, 2017
    Assignee: NXP USA, INC.
    Inventors: Philippe Renaud, Bruce Green
  • Integrated circuit charge pump with failure protection
    Patent number: 9819260
    Abstract: Disclosed is a charge pump protection device including a power supply voltage, a charge pump to produce an output voltage higher than the power supply voltage, the charge pump including, a pumping capacitor to store voltage during a charging state and to discharge the voltage during a pumping state thereof, a plurality of switches to regulate the charging and pumping states, a charge pump capacitor to store the output voltage, and at least one current limiter in series with at least one of the plurality of switches to limit current and prevent an electrical failure of the charge pump.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: November 14, 2017
    Assignee: NXP B.V.
    Inventors: Derk Jan Hissink, Jacobus Govert Sneep, Fred Mostert, Hendrikus van Iersel
  • Devices and methods for testing integrated circuit devices
    Patent number: 9818656
    Abstract: A method of testing includes attaching a first and second die to first and second die sites of a lead frame and forming a plurality of wire bonds coupling a plurality of pins of the first die site to the first die and a plurality of pins of the second die site to the second die. The first and second die are encapsulated. An isolation cut is performed to isolate the plurality of pins of the first die site from the plurality of pins of the second die site, while maintaining electrical connection between the first tie bar of the first die site and the first tie bar of the second die site. The first and second die are tested while providing a first power supply source to the first and second die via the first tie bars. After testing, the dies sites are fully singulated to result in packaged IC device.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: November 14, 2017
    Assignee: NXP USA, Inc.
    Inventors: Mark Edward Schlarmann, Dwight Lee Daniels, Stephen Ryan Hooper, Chad Dawson, Fengyuan Li
  • Power supply circuit using DC/DC converter
    Patent number: 9819276
    Abstract: A power supply circuit comprises an input for receiving a power supply from a battery and a DC/DC converter for supplying a converted voltage to a load. A regulator is used for controlling the DC/DC converter such that the current drawn from the converter is smoothed. A charge storage device at the output of the DC/DC converter enables delivery of a non-constant current to the load.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: November 14, 2017
    Assignee: NXP B.V.
    Inventors: Dave Kroekenstoel, Steven Thoen
  • mm-Wave frequency peak detector
    Patent number: 9817041
    Abstract: A peak detector circuit comprises a first output coupled to ground by a first load and to emitter terminals of first and second switching devices. A second output is coupled to ground by a second load and to emitter terminals of third and fourth switching devices. A third output is coupled to a supply voltage node by a third load and to collector terminals of the first and second switching devices. A fourth output is coupled to the supply voltage node by a fourth load and to collector terminals of the third and fourth switching devices. The first, second, third, and fourth switching devices have control terminals which are biased with a common bias voltage. The first, second, third and fourth load are selected so that R1=R2=?f*R3=?f*R4, with R1, R2, R3, R4 being a resistance of the first, second, third and fourth loads, respectively, and ?f a common-base current gain of the switching devices.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: November 14, 2017
    Assignee: NXP USA, Inc.
    Inventor: Yi Yin
  • Method and apparatus for determining feasibility of memory operating condition change using different back bias voltages
    Patent number: 9817601
    Abstract: A memory device having at least one output predicting a feasibility of whether the memory device will work properly at a different operating condition including a different supply voltage and/or a different operating frequency than the current supply voltage and/or the current operating frequency. A semiconductor device (e.g. a SoC chip) provides a test to either validate or invalidate the feasibility for the memory device to enter such a different operating condition based on read and write operations of the memory device in normal access cycles. The memory device is partitioned with at least a first memory unit and a second memory unit, which can be coupled to different back-bias voltages. This operating condition predicting function can be enabled or disabled by the semiconductor device in real time operation depending on the feasibility test results.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: November 14, 2017
    Assignee: NXP USA, INC.
    Inventors: Shayan Zhang, Nihaar Mahatme, Rakesh Pandey
  • Transferring a descriptive web interface language code between two nearfield communication devices
    Patent number: 9820081
    Abstract: It is described a method for a wireless Near Field Communication (NFC) between a NFC enabled device (110) and a NFC capable mobile telecommunication end device (120). The provided method comprises transferring data from the NFC enabled device (110) to the NFC capable mobile telecommunication end device (120). Thereby, at least some of the transferred data represent a code in a descriptive web interface language. Further, a NFC capable mobile telecommunication end device (120) and a NFC enabled device (110) are described for participating in such a NFC method. Furthermore, a system (100) comprising such a NFC enabled device (110) and such a NFC capable mobile telecommunication end device (120) and a computer program for enabling such a NFC method are described.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: November 14, 2017
    Assignee: NXP B.V.
    Inventor: Juergen Schroeder
  • Circuit for reducing negative glitches in voltage regulator
    Patent number: 9819332
    Abstract: A circuit that stabilizes an output signal of a voltage regulator includes a glitch amplifier, a pulse generator, and a transistor. The glitch amplifier amplifies glitches in the output signal and generates a glitch amplifier output signal. The pulse generator receives the glitch amplifier output signal and generates a control signal. When there is a positive glitch in the output signal and a voltage level of the glitch amplifier output signal is less than a first threshold voltage, the pulse generator deactivates the control signal, which turns off the transistor. When there is a negative glitch in the output signal and the voltage level of the glitch amplifier output signal is greater than a second threshold voltage, the pulse generator activates the control signal, which turns on the transistor and provides a compensating current surge to reduce a voltage droop in the output signal.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: November 14, 2017
    Assignee: NXP USA, INC.
    Inventors: Ashish Ojha, Parul K. Sharma
  • System and method for stereo widening
    Patent number: 9820075
    Abstract: The present disclosure relates to a system for and method of stereophonic widening in loudspeakers. The method includes the steps of: monitoring an amplifier state and/or loudspeaker state; generating an effect control signal in response to monitoring the amplifier state and/or a loudspeaker state; applying the effect control signal to an effect processor. The effect processor controls an amount of stereophonic widening based on the effect control signal.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: November 14, 2017
    Assignee: NXP B.V.
    Inventor: Christophe Marc Macours
  • Controller for a power converter
    Patent number: 9819264
    Abstract: A controller for a power converter. The power converter comprises a converter-switch and a converter-inductor. The controller comprises a controller-output-terminal configured to provide a switch-control-signal for the converter-switch, a comparator and a delay-block. The comparator can provide a comparator-output-signal that has a comparator-output-state dependent on whether or not a sensed-signal is greater than a reference-signal, wherein the comparator-output-state can take a first-state-value or a second-state-value. The delay-block can: set a time-delay-value based on: (i) a voltage across the converter-inductor; start a timer when the comparator-output-state changes; and cause a change in the switch-control-signal when the timer reaches the time-delay-value.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: November 14, 2017
    Assignee: NXP B.V.
    Inventor: Hendrik Boezen
  • CAN FD end-of-frame detector, CAN bit stream processing device, method for detecting the end of a CAN FD frame, and method of operating a CAN bit stream processor
    Patent number: 9819589
    Abstract: A CAN FD frame comprises one or more portions provided at a normal bit rate that includes an end-of-frame field consisting of a succession of at least seven recessive bits. A method for detecting the end-of-frame of a CAN FD frame in an input bit stream entails providing a recessive bit count; defining a stretched bit transmission time longer than the bit transmission time associated with the high data rate; stretching the bit transmission time of each dominant bit succeeding a recessive bit in the input bit stream to the stretched bit transmission time to generate a conditioned input bit stream; sampling the conditioned input bit stream at a bit counter rate to generate a sampled bit stream; resetting the recessive bit count in response to each dominant bit in the sampled bit stream; and incrementing the recessive bit count in response to each recessive bit in the sampled bit stream.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 14, 2017
    Assignee: NXP USA, Inc.
    Inventor: Robert Gach
  • Multi-port transmitter device for transmitting at least partly redundant data, an associated control system, an associated method and an associated computer program product
    Patent number: 9817784
    Abstract: A multi-port transmitter device for transmitting at least partly redundant data is described. The multi-port transmitter device comprises at least two transmitters comprising respective transmitter buffers. One transmitter is a master transmitter that issues a request to the processor to provide a data block when the transmitter buffer of the master transmitter has free space to store a data block. The processor is arranged to copy at least one data block of data stored in an external memory from the external memory to respective positions in a local buffer. The processor is arranged to, in accordance with a predefined sequence, sequentially initiate transfer of the data block from the respective position of the data block in the local buffer to the transmitter buffers of the at least two transmitters in response to a request from the master transmitter to provide a data block.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: November 14, 2017
    Assignee: NXP USA, Inc.
    Inventor: Graham Edmiston
  • Antenna system
    Patent number: 9819097
    Abstract: A near-field electromagnetic induction antenna including: an electric antenna including a plate; a first feeding connection and a second feeding connection; and a magnetic antenna including a first coil and a second coil, wherein the first coil and the second coil are mutually coupled, wherein a first connection of the first coil is connected to the first feeding connection, wherein a second connection of the first coil and a first connection of the second coil is connected to the second feeding connection, and wherein a second connection of the second coil is connected to the plate.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: November 14, 2017
    Assignee: NXP B.V.
    Inventors: Anthony Kerselaers, Liesbeth Gomme
  • Integrated circuit and manufacturing method
    Patent number: 9818905
    Abstract: Disclosed is an integrated circuit comprising a substrate (10); and an optical CO2 sensor comprising: first and second light sensors (12, 12?) on said substrate, said second light sensor being spatially separated from the first light sensor; and a layer portion (14) including an organic compound comprising at least one amine or amidine functional group over the first light sensor; wherein said integrated circuit further comprises a signal processor (16) coupled to the first and second light sensor for determining a difference in the respective outputs of the first and second light sensor. An electronic device comprising such a sensor and a method of manufacturing such an IC are also disclosed.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: November 14, 2017
    Assignee: NXP B.V.
    Inventors: Aurelie Humbert, Roel Daamen, Youri Victorovitch Ponomarev