Abstract: A communication unit comprises a modem configured to generate a first and second test digital quadrature signal. The modem is configured to: estimate a first sampling error performance associated with a first quadrature path from the first received test digital quadrature signal; estimate a second sampling error performance associated with a second quadrature path from the second received test digital quadrature signal; and generate at least one sampling error compensation signal based on the first estimated sampling error performance and second estimated sampling error performance to be applied to at least one of the receiver and transmitter.

Abstract: A device includes a near field communication (NFC) circuit that is configured and arranged to communicate data with external devices. An internal communication circuit communicates data over a microprocessor bus. A secure memory circuit stores an identifier that is unalterable in the secure memory circuit. Logic circuitry performs a secure transaction protocol.

Abstract: A electromagnetic induction wireless communication system including: a magnetic antenna; an electric antenna; a tuning capacitor coupled to the antenna combination configured to tune the antenna combination; a controller configured to control the operation of the communication system; a signal source coupled to the controller configured to produce a communication signal used to drive the magnetic antenna and the electric antenna; a voltage control unit coupled to the signal source configured to produce one of an amplitude difference, phase difference, and an amplitude and a phase difference between the communication signal used to drive the magnetic antenna and electric antenna.

Abstract: A method of packaging a semiconductor die includes the steps of mounting the semiconductor die on a carrier, electrically connecting electrical contact pads of the semiconductor die to external electrical contacts, and encapsulating the die with a mold compound to form a packaged die. The packaged die is then thinned by using a dicing saw blade to trim the mold compound off of the top, non-active side of the package using a series of vertical cuts. This thinning step can be performed at the same time as a normal dicing step so no additional equipment or process steps are needed. Further, packages of varying thicknesses can be assembled simultaneously.

Abstract: Embodiments of a method and a system for processing a radio frequency (RF) signal are disclosed. In an embodiment, a method for processing an RF signal involves down-converting the RF signal into a converted signal, obtaining a received signal strength indicator (RSSI) value based on an amplitude of the RF signal, and amplifying the converted signal based on the RSSI value.

Abstract: Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil.

Abstract: A transistor circuit includes a transistor having a control electrode, a first current electrode, and a second current electrode. A turn off mode change circuit has a signal input that receives a series of pulses, an output coupled to the control electrode of the transistor, and a control input. The turn off mode change circuit has a fast turn off mode and a slow turn off mode. A turn off mode detection circuit is coupled between the first current electrode and the second current electrode. The turn off mode change circuit detects when a transition from the fast turn off mode to the slow turn off mode is desired and when a transition from the slow turn off mode to the fast transition mode may be performed.

Abstract: According to an aspect of the invention, an electronic lock is conceived, being adapted to harvest energy from a radio frequency (RF) connection established between a mobile device and said electronic lock, further being adapted to use the harvested energy for processing an authorization token received via said RF connection from the mobile device, and further being adapted to use the harvested energy for controlling an unlocking switch in dependence on a result of said processing.

Abstract: An integrated circuit comprises a first functional unit and one or more other functional units. The first functional unit has an input for receiving data and an output for providing data. The integrated circuit tests and operates the first functional unit. Testing comprises: connecting the input of the first functional unit to the output of the first functional unit, thereby generating a loopback path from the output of the first functional unit to the input of the first functional unit; loading a test pattern onto the first functional unit; feeding a test clock signal comprising one or more clock edges, thereby prompting the first functional unit to transform the test pattern; and reading the transformed test pattern. Operating the first functional unit comprises: connecting the input of the first functional unit to an output of the other functional units; and feeding a normal clock signal to the first functional unit.

Abstract: High resolution tuning of the phase for active load modulation (ALM) in a near field communication (NFC) system is desirable for optimizing the load modulation amplitude. The present disclosure describes that, in one embodiment, high resolution tuning of the phase can be achieved by adjusting the attenuation factor of a radio frequency (RF) attenuator in the NFC system.

Abstract: A method is provided, which includes identifying a data transfer rate associated with a wireless communication device. The data transfer rate is identified from a group including a legacy data transfer rate and a plurality of non-legacy data transfer rates. In response to identification of a selected non-legacy data transfer rate, a selected non-legacy modulation scheme is identified, which is associated with the selected non-legacy data transfer rate. Modulation of a data payload is performed according to the selected non-legacy modulation scheme. A non-legacy header structure is formed that includes a non-legacy start-of-frame delimiter (SFD) and an identifier of the selected non-legacy modulation scheme. Modulation of the non-legacy header structure is performed according to the legacy modulation scheme.

Abstract: An integrated circuit (IC) having a memory for storing data also has a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of the memory. A test interface provides test data. Flip-flops of the IC are connected together into at least one serial scan chain. The test interface unit receives test data including MBIST configuration data. The MBIST unit, in a first mode, tests the memory based on the MBIST configuration data at least partly in parallel with a scan test using the scan chain. Thus, both the memory and the logic circuitry can be tested in parallel.

Abstract: An integrated circuit includes a first transistor including a first current electrode, a second current electrode, and a bulk tie; a first conductive line coupled between the first current electrode and a first supply voltage; and a second conductive line coupled to the second current electrode. A resistance of the second conductive line is at least 5 percent greater than a resistance of the first conductive line. The bulk tie is coupled to a second supply voltage. The first supply voltage is different than the second supply voltage.

Abstract: There is described a method of checking whether a transponder device (220) is in proximity of a reader device (210), the method comprising (a) transmitting a first command (331) from the reader device to the transponder device, (b) in response to receiving the first command at the transponder device, transmitting a first response (332) to the reader device, the first response including an expected transponder device response time (pubRespTime) which is stored in a memory (224) of the transponder device, (c) transmitting a second command (333) from the reader device to the transponder device, (d) in response to receiving the second command at the transponder device, transmitting a second response (334) to the reader device, (e) at the reader device, determining the transponder device response time as the difference in time between transmitting the second command and receiving the second response from the transponder device, and (f) determining whether the determined transponder device response time matches the

Abstract: A data logging system for logging input data received from a data source is described. The data logging system has a data storage memory. A data input is arranged to repeatedly receive input data having a temporal input data resolution. A write controller is arranged to write newly received input data as received via the data input into the data storage memory. The writing comprises writing the newly received input data at the temporal input data resolution. The writing comprises keeping recent data at the temporal input data resolution in the data storage memory, and overwriting part of old data with newly received input data while keeping another part of the old data in the data storage memory at lower data resolution.

Abstract: A system for providing a first voltage generated by a main supply and a second voltage generated by a battery to an integrated circuit (IC) includes supply-selection, control logic and switching circuits. The supply-selection circuit includes first, second, and third transistors. The switching circuit includes fourth and fifth transistors that supply the first and second voltages to the IC when switched on. The supply-selection circuit selects and provides the higher of the first and second voltages to body terminals of the fourth and fifth transistors for maintaining required body-bias voltage conditions. The control logic circuit generates a first control signal as long as the first voltage is within a predetermined range for keeping the fourth transistor switched on and a second control signal when the first voltage is not within the predetermined range for switching on the fifth transistor to supply the second voltage.

Abstract: A register file module comprising at least one register array comprising a plurality of latch devices is described. The plurality of latch devices is arranged to individually provide memory bit-cells when the register file module is configured to operate in a first, functional operating mode, and at least one clock control component is arranged to receive a clock signal and to propagate the clock signal to the latch devices within the at least one register array. The register file module is configurable to operate in a second, scan mode in which the latch devices within the at least one register array are arranged into at least one scan chain. The at least one clock control component is arranged to propagate the clock signal to the latch devices within the at least one register array such that alternate latch devices within the at least one scan chain receive an inverted form of the clock signal.

Abstract: In an embodiment there is: negative voltage generator configured to generate an output having a negative voltage from an input having a positive voltage comprising an input node configured to receive an alternating signal, an output node for outputting an output voltage of the generator and a ground node, a switching element configured to provide a conductive and non-conductive flow path between a first terminal and a second terminal in response to a control signal; a control element adapted to control the flow of current therethrough between a first terminal and a second terminal.

Abstract: A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The structure also includes a substrate having a cavity, wherein the cavity is defined by a vertical portion and a horizontal portion, wherein the vertical portion surrounds the first device, the horizontal portion is over the first device, and the first device is between the horizontal portion and the first major surface of the interconnect layer such that the first device is in the cavity. The structure further includes a second microelectronic device attached to the horizontal portion of the substrate, and encapsulant on the interconnect layer and surrounding the first device, the substrate, and the second device, such that the substrate is embedded in the encapsulant.

Abstract: A system includes a MEMS sensor having dual proof masses capable of moving independently from one another in response to forces imposed upon the proof masses. Each proof mass includes an independent set of sense contacts configured to provide output signals corresponding to the physical displacement of the corresponding sense mass. A switch system is in communication with the sense contacts. The switch system is configured to enable a sense mode and various test modes for the MEMS sensor. When the switch system enables a sense mode, output signals from the sense contacts can be combined to produce sense signals. When the switch system enables a test mode, the second contacts are electrically decoupled from one another to disassociate the output signals from one another. The independent sense contacts and switch system enable the concurrent compensation and calibration of the proof masses along two different sense axes.