Patents Assigned to NXP
  • Patent number: 9800213
    Abstract: The embodiments described herein provide an amplifier device that utilizes bonding pad capacitance in an impedance matching network. In one specific embodiment, the amplifier device comprises: an amplifier formed on a semiconductor die, the amplifier including an amplifier input and an amplifier output, the amplifier configured to generate an amplified radio frequency (RF) signal at the amplifier output; and an impedance matching network coupled to the amplifier, the impedance matching network including a capacitor, where the capacitor includes a first plate, a second plate, and dielectric material between the first and second plates, where the first plate includes or is directly electrically coupled to a bond pad on the semiconductor die.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: October 24, 2017
    Assignee: NXP USA, INC.
    Inventors: Ibrahim Khalil, Ebrahim M. Al Seragi, Jeffrey K. Jones
  • Patent number: 9798294
    Abstract: A system for detecting tampering in a product having a tamper-detector seal, including a secure element configured to store a digital signature and a data associated with the digital signature, transmit the digital signature and the data associated with the digital signature in response to a request, detect tampering of the tamper-detector seal, and modify the data associated with the digital signature if tampering is detected. The system further includes a seal validation device configured to receive a public key associated with the product, request the digital signature and the data associated with the digital signature from the secure element, and validate the digital signature utilizing the data associated with the digital signature and the public key associated with the product.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: October 24, 2017
    Assignee: NXP B.V.
    Inventors: Shlomo Markel, Jacob Mendel
  • Patent number: 9799760
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: October 24, 2017
    Assignee: NXP USA, INC.
    Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
  • Patent number: 9800554
    Abstract: According to an aspect of the invention, a method for establishing secure communication between nodes in a network is conceived, wherein the network comprises a key manager which accommodates a key-manager-specific public key and a corresponding key-manager-specific private key; wherein a copy of the key-manager-specific public key is stored in an installation device; wherein the installation device provides a new node with the copy of the key-manager-specific public key; and wherein said new node is registered with the key manager by providing a node-specific public key and an identifier of said new node to the key manager, such that other nodes in the network may setup end-to-end secure connections with said new node by requesting the node-specific public key of said new node from the key manager.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: October 24, 2017
    Assignee: NXP B.V.
    Inventors: Timo van Roermund, Ewout Brandsma, Maarten Christiaan Pennings
  • Patent number: 9799757
    Abstract: A sensor device (100, 2800) for detecting particles, the sensor device (100, 2800) comprising a substrate (102), a first doped region (104) formed in the substrate (102) by a first dopant of a first type of conductivity, a second doped region (106, 150) formed in the substrate (102) by a second dopant of a second type of conductivity which differs from the first type of conductivity, a depletion region (108) at a junction between the first doped region (104) and the second doped region (106, 150), a sensor active region (110) adapted to influence a property of the depletion region (108) in the presence of the particles, and a detection unit (112) adapted to detect the particles based on an electric measurement performed upon application of a predetermined reference voltage between the first doped region (104) and the second doped region (106, 150), the electric measurement being indicative of the presence of the particles in the sensor active region (110).
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: October 24, 2017
    Assignee: NXP B.V.
    Inventors: Evelyne Gridelet, Almudena Huerta, Pierre Goarin, Jan Sonsky
  • Patent number: 9799629
    Abstract: Aspects of the disclosure are directed to integrated circuit dies and their manufacture. In accordance with one or more embodiments, a plurality of integrated circuit dies are provided in a semiconductor wafer, with each integrated circuit die having: an integrated circuit within the die, a via extending from a first surface to a second surface that opposes the first surface, and first and second electrical contacts at the first surface respectively coupled to the via and to the integrated circuit. Lanes are created in a front side of the wafer between the dies, and a portion of the back side of the wafer is removed to expose the lanes. A further contact and/or via is also exposed at the backside, with the via providing an electrical signal path for coupling electrical signals through the integrated circuit die (e.g., bypassing circuitry therein).
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: October 24, 2017
    Assignee: NXP B.V.
    Inventor: Jeroen Johannes Maria Zaal
  • Patent number: 9800208
    Abstract: An embodiment of a radio-frequency (RF) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. The surface-mountable capacitor is coupled in a shunt configuration between the at least one transistor and a power supply terminal of the device to decouple the at least one transistor from a power supply.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: October 24, 2017
    Assignee: NXP USA, INC.
    Inventors: Mahesh K. Shah, Jerry L. White, Li Li, Hussain H. Ladhani, Audel A. Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos
  • Patent number: 9798550
    Abstract: A method and device for memory access in processors is provided. A processor, comprising a plurality of computational units, is capable of executing a single instruction on multiple pieces of data simultaneously (SIMD). A read operation is initiated to load data from memory into the plurality of computational units (CUs) arranged into a plurality of CU groups. The memory is arranged into a plurality of memory macro-blocks each associated with a respective CU group of the plurality of CU groups. For each CU group a respective first memory address is determined and for each CU group, the data in the associated memory macro-block is accessed at the respective first memory address.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: October 24, 2017
    Assignee: NXP USA, Inc.
    Inventors: Malcolm Stewart, Ali Osman Ors, Daniel Laroche
  • Patent number: 9799617
    Abstract: Methods for repacking copper wire bonded microelectronic die (that is, die having bond pads bonded to copper wire bonds) are provided. In one embodiment, the repackaging method includes the step or process of obtaining a microelectronic package containing copper wire bonds and a microelectronic die, which includes bond pads to which the copper wire bonds are bonded. The microelectronic die is extracted from the microelectronic package in a manner separating the copper wire bonds from the bond pads. The microelectronic die is then attached or mounted to a Failure Analysis (FA) package having electrical contact points thereon. Electrical connections are then formed between the bond pads of the microelectronic die and the electrical contact points of the FA package at least in part by printing an electrically-conductive material onto the bond pads.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 24, 2017
    Assignee: NXP USA, Inc.
    Inventors: Mitchell Curiel, Huan Gim Chan, Wan Foong Kho
  • Patent number: 9798338
    Abstract: Embodiments of power source circuits and methods for operating a power source circuit are described. In one embodiment, a method for operating a power source circuit involves receiving at the power source circuit at least one digital signal from a feedback loop and increasing or decreasing an output power signal of the power source circuit in response to the at least one digital signal. Other embodiments are also described.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: October 24, 2017
    Assignee: NXP B.V.
    Inventor: Remco Van de Beek
  • Patent number: 9799580
    Abstract: A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: October 24, 2017
    Assignee: NXP USA, INC.
    Inventors: Li Li, Jaynal A. Molla, Lakshminarayan Viswanathan
  • Patent number: 9798901
    Abstract: A device securely accesses data in a memory via an addressing unit which provides a memory interface for interfacing to a memory, a core interface for interfacing to a core processor and a first and second security interface. The device includes a security processor HSM for performing at least one security operation on the data and a remapping unit MMAP. The remapping unit enables the security processor to be accessed by the core processor via the first security interface and to access the memory device via the second security interface according to a remapping structure for making accessible processed data based on memory data. The device provides a clear view on encrypted memory data without requiring system memory for storing the clear data.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: October 24, 2017
    Assignee: NXP USA, Inc.
    Inventors: Juergen Frank, Michael Staudenmaier, Manfred Thanner
  • Patent number: 9798228
    Abstract: Consistent with an example embodiment, there is a semiconductor wafer substrate comprising a plurality of integrated circuits formed in arrays of rows and columns on the wafer substrate. A plurality of integrated circuits are in arrays of rows and columns on the wafer substrate; the rows and the columns have a first width. First and second saw lanes separate the integrated circuits, the first saw lanes are arranged parallel and equidistant with one another in a first direction defined by rows, and the second saw lanes are arranged parallel and equidistant with one another in a second direction defined by the columns. A plurality of process modules (PM) are on the wafer substrate, the PM modules defined in an at least one additional row/column having a second width. The at least one additional row/column is parallel to the plurality of device die in one direction.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: October 24, 2017
    Assignee: NXP B.V.
    Inventors: Hans Cobussen, Tonny Kamphuis, Heimo Scheucher, Laurentius de Kok
  • Patent number: 9800223
    Abstract: A bulk-acoustic-mode MEMS resonator has a first portion with a first physical layout, and a layout modification feature. The resonant frequency is a function of the physical layout, which is designed such that the frequency variation is less than 150 ppm for a variation in edge position of the resonator shape edges of 50 nm. This design combines at least two different layout features in such a way that small edge position variations (resulting from uncontrollable process variation) have negligible effect on the resonant frequency.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: October 24, 2017
    Assignee: NXP B.V.
    Inventors: Joep J. M. Bontemps, Jan Jacob Koning, Casper van der Avoort, Jozef Thomas Martinus van Beek
  • Patent number: 9790089
    Abstract: A MEMS sensor package comprises a MEMS die that includes a substrate having a sensor formed thereon and a cap layer coupled to the substrate. The cap layer has a cavity overlying a substrate region at which the sensor resides. A port extends between the cavity and a side wall of the MEMS die and enables admittance of fluid into the cavity. Fabrication methodology entails providing a substrate structure having sensors formed thereon, providing a cap layer structure having inwardly extending cavities, and forming a channel between pairs of the cavities. The cap layer structure is coupled with the substrate structure and each channel is interposed between a pair of cavities. A singulation process produces a pair of sensor packages, each having a port formed by splitting the channel, where the port is exposed during singulation and extends between its respective cavity and side wall of the sensor package.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: October 17, 2017
    Assignee: NXP USA, Inc.
    Inventors: Chad S. Dawson, Stephen R. Hooper, Fengyuan Li, Arvind S. Salian
  • Patent number: 9790082
    Abstract: A device comprises a silicon-on-insulator (SOI) substrate having first and second silicon layers with an insulator layer interposed between them. A structural layer, having a first conductivity type, is formed on the first silicon layer. A well region, having a second conductivity type opposite from the first conductivity type, is formed in the structural layer, and resistors are diffused in the well region. A metallization structure is formed over the well region and the resistors. A first cavity extends through the metallization structure overlying the well region and a second cavity extends through the second silicon layer, with the second cavity stopping at one of the first silicon layer and the insulator layer. The well region interposed between the first and second cavities defines a diaphragm of a pressure sensor. An integrated circuit and the pressure sensor can be fabricated concurrently on the SOI substrate using a CMOS fabrication process.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: October 17, 2017
    Assignee: NXP USA, Inc.
    Inventors: Lianjun Liu, Amitava Bose
  • Patent number: 9792981
    Abstract: A non-volatile memory includes a first bit cell having a programmable resistive element coupled to a write bit line wherein the programmable resistive element is programmable to one of two resistive states, a resistive element coupled to the programmable resistive element at a circuit node, and a first transistor configured to operate in saturation during a read operation. The first transistor has a control electrode coupled to the circuit node and a first current electrode coupled to a read bit line.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: October 17, 2017
    Assignee: NXP USA, Inc.
    Inventors: Perry H. Pelley, Frank K. Baker, Jr.
  • Patent number: 9791340
    Abstract: During a first cycle of operation, first and second bottom electrodes of a split bottom electrode are electrically connected together. A total capacitance between the split bottom electrode and a top electrode layer is measured to determine the ambient pressure. Accordingly, pressure, e.g., tire pressure, is measured during the first cycle of operation. In a second cycle of operation, the first and second bottom electrodes are electrically disconnected. A first capacitance between the first bottom electrode and top electrode layer and a second capacitance between second bottom electrode and top electrode layer are measured. The difference between the first capacitance and the second capacitance is calculated and compared to a fault indicating capacitance variation to determine if the pressure sensor device is operating normally or malfunctioning. Accordingly, a self-test of the pressure sensor device is performed during the second cycle of operation.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: October 17, 2017
    Assignee: NXP USA, Inc.
    Inventors: Dubravka Bilic, Chad S Dawson
  • Patent number: 9793348
    Abstract: A method of manufacturing a semiconductor device includes forming trench isolation structures, exposing some of the trench isolation structures 28 to leave others 30 masked, and then selectively etching a buried layer to form a cavity 32 under an active device region 34. The active device region 34 is supported by support regions in the exposed trenches 28. The buried layer may be a SiGe layer on a Si substrate.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: October 17, 2017
    Assignee: NXP B.V.
    Inventor: Jan Sonsky
  • Patent number: 9794934
    Abstract: Embodiments of a method for communicating in a wireless mesh network, a method for communicating in a Bluetooth Low Energy (BLE) mesh network, and a wireless communications device are described. In one embodiment, a method for communicating in a wireless mesh network involves at a first wireless communications device, scanning the wireless mesh network for a unit time period to discover a first transmission time slot within the unit time period that is used by a second wireless communications device in the wireless mesh network, at the first wireless communications device, choosing a second transmission time slot within the unit time period for the first wireless communications device, where the second transmission time slot is different from the first transmission time slot, and from the first wireless communications device, broadcasting data in the wireless mesh network in the second transmission time slot within a subsequent unit time period.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: October 17, 2017
    Assignee: NXP B.V.
    Inventors: Yifeng Zhang, Tao Zhang, Tianbao Liang, Shuchen Xie, Fuquan Zhang, Jianjun Zhang