Patents Assigned to NXP
  • Patent number: 9786585
    Abstract: One example discloses a lead-frame, comprising: a die-pad having a die coupling surface; a set of terminals each having an outer terminal edge and an inner terminal edge; wherein the outer terminal edge faces away from the die-pad and the inner terminal edge faces toward the die-pad; and a terminal connector having a first side coupled to the inner terminal edge and a second side coupled to the die-pad.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: October 10, 2017
    Assignee: NXP B.V.
    Inventor: Pieter Offeringa
  • Patent number: 9786770
    Abstract: A semiconductor device that includes a semiconductor structure having a side wall that is non planar and that extends farther outward at an upper portion than at a lower portion of the side wall. The semiconductor structure extends underneath a semiconductor layer wherein a top portion of the structure contacts the semiconductor layer.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: October 10, 2017
    Assignee: NXP USA, INC.
    Inventors: Jay Paul John, Vishal Trivedi, James Albert Kirchgessner
  • Patent number: 9786108
    Abstract: A device is disclosed. The device includes a processor and a memory. The memory is coupled to the processor and having programming instructions to operate a vehicle via Near Field Communication (NFC). The device also includes a NFC controller coupled to a short range antenna, a passive NFC tag and a secure memory coupled to the NFC controller for storing a security code.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: October 10, 2017
    Assignee: NXP B.V.
    Inventors: Bernhard Spiess, Ulrich Neffe
  • Patent number: 9784787
    Abstract: An electric field sensor includes sense and reference cells. The sense cell produces a resistance that varies relative to an intensity of an electric field, and the reference cell produces a resistance that is invariable relative to the intensity of the electric field. An output signal indicative of the intensity of the electric field is determined using the difference between the resistances. A system includes an electric field source that outputs a digital test program as an electric field signal. The system further includes the electric field sensor formed with IC dies on a wafer. The electric field sensor receives the electric field signal. The received electric field signal is converted to the test program, and the test program is stored in memory on the wafer. The electric field source does not physically contact the dies, but can flood an entire surface of the wafer with the electric field signal.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: October 10, 2017
    Assignee: NXP USA, Inc.
    Inventors: Lianjun Liu, Philippe Bernard Roland Lance, David Joseph Monk, Babak A Taheri
  • Patent number: 9785368
    Abstract: A system for mapping control and user data includes a direction scanner, an address calculator, a collision detector, a buffer, and a mapper for mapping control and user data from a first memory to a second memory. The direction scanner determines the highest priority value of to a code word index. The address calculator calculates start and end addresses of the highest priority value. When an address from an address range, defined by the start and end addresses, is already mapped to other control data, the collision detector detects a collision and generates feedback data. The address calculator outputs modified start and end addresses based on the feedback data. When no collision is detected, the address calculator outputs the modified start and end addresses to the buffer. The mapper then maps the control and user data to the modified start and end addresses in the second memory.
    Type: Grant
    Filed: July 24, 2016
    Date of Patent: October 10, 2017
    Assignee: NXP USA, INC.
    Inventors: Ritika Sharma, Somvir Dahiya, Arvind Kaushik, Amrit P. Singh
  • Patent number: 9786515
    Abstract: A semiconductor device package and method of manufacturing is provided. An interconnect pre-assembly includes a first frame having a plurality of first signal conduits affixed to a second frame having a plurality of second signal conduits embedded in a second substrate forming an electrical coupling between one or more first signal conduits and one or more of the second signal conduits. One or more conductive balls are connected to the one or more second signal conduits. The interconnect pre-assembly is placed over a semiconductor die, having at least one of the first conductive balls disposed over the semiconductor die. An encapsulant encapsulates the interconnect pre-assembly, the semiconductor die, and the one or more conductive balls, such that a portion of the one or more first conductive balls is exposed at a top surface of the encapsulant.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: October 10, 2017
    Assignee: NXP USA, INC.
    Inventor: Weng Foong Yap
  • Publication number: 20170289931
    Abstract: Embodiments of a method and a system for processing a radio frequency (RF) signal are disclosed. In an embodiment, a method for processing an RF signal involves down-converting the RF signal into a converted signal, obtaining a received signal strength indicator (RSSI) value based on an amplitude of the RF signal, and amplifying the converted signal based on the RSSI value.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Applicant: NXP B.V.
    Inventors: Stefan Mendel, Michael Pieber
  • Publication number: 20170288916
    Abstract: Embodiments of a method and a system controlling an amplifier of a communications device are disclosed. In an embodiment, a method for controlling an amplifier of a communications device involves checking for a data reception at the communications device and freezing a gain of the amplifier if the data reception is detected.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Applicant: NXP B.V.
    Inventors: Stefan Mendel, Michael Pieber
  • Publication number: 20170288543
    Abstract: Embodiments of a circuit for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter are disclosed. The circuit includes a ripple generation circuit coupled to a reference voltage input and to a sense voltage input, and having a reference voltage output to form a main loop. The circuit also includes a DC error correction circuit connected between the reference voltage input and the sense voltage input, and the reference voltage output of the ripple generation circuit. The DC error correction circuit includes a coarse DC error correction loop coupled between the sense voltage input and the reference voltage output and a fine DC error correction loop coupled between the reference voltage input and the reference voltage output. A method for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter, is also disclosed.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Applicant: NXP B.V.
    Inventors: Yue Jing, Ahmad Dashtestani, Shufan Chan
  • Publication number: 20170288795
    Abstract: Embodiments of a method and a system for generating a received signal strength indicator (RSSI) value that corresponds to a radio frequency (RF) signal are disclosed. In an embodiment, a method for generating an RSSI value that corresponds to an RF signal involves obtaining an attenuation factor code in response to applying an automatic gain control (AGC) operation to the RF signal, obtaining an analog-to-digital converter (ADC) code in response to applying an ADC operation to a signal that results from the AGC operation, and combining the attenuation factor code and the ADC code to generate an RSSI value. Other embodiments are also described.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Applicant: NXP B.V.
    Inventors: Jingfeng Ding, Helmut Kranabenter, Stefan Mendel, Gernot Hueber, Josef Zipper
  • Publication number: 20170285996
    Abstract: In an embodiment, a method for re-programming memory is disclosed. In the embodiment, the method involves selecting a memory page based on version information and re-programming the selected memory page using cyclic redundancy check (CRC) data for the memory page.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 5, 2017
    Applicant: NXP B.V.
    Inventors: SÖNKE OSTERTUN, Wolfgang STIDL, Raffaele COSTA
  • Publication number: 20170288537
    Abstract: Embodiments of a circuit for use with a DC-DC converter are disclosed. In an embodiment, a circuit for controlling frequency variation for a ripple based, constant-on time DC-DC converter, is discloses. The circuit includes a set/reset (SR) latch, a comparator configured to set the SR latch, and an on-time and frequency variation controller configured to reset the SR latch. The on-time and frequency variation controller includes a feedback loop configured to increase the rate at which a ramp voltage increases to reduce the time it takes for the ramp voltage to exceed a threshold voltage. Embodiments of a method for controlling frequency variation for a ripple based, constant-on time DC-DC converter are also disclosed.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Applicant: NXP B.V.
    Inventors: Yue Jing, Ahmad Dashtestani, Shufan Chan
  • Publication number: 20170288531
    Abstract: Embodiments of a charge pump circuit and a method for operating a charge pump circuit are disclosed. In an embodiment, a charge pump circuit includes a charge pump configured to generate a charge pump output voltage, a transistor array including multiple transistor devices that includes at least one transistor device having a back gate terminal coupled to the charge pump output voltage, and a control circuit configured to control the charge pump output voltage so as to regulate the back bias voltage of the transistor devices within the transistor array. Other embodiments are also described.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Applicant: NXP B.V.
    Inventor: Ivan Carlos Ribeiro do Nascimento
  • Patent number: 9779988
    Abstract: A semiconductor device includes a semiconductor substrate having an inactive area and a pair of active areas separated by the inactive area, a control terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area to define a conduction path during operation between a first conduction region in each active area and a second conduction region in each active area, a conduction terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area for electrical connection to each first conduction region, and a via extending through the semiconductor substrate, electrically connected to the conduction terminal, and positioned in the inactive area.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: October 3, 2017
    Assignee: NXP USA, INC.
    Inventors: Darrell G. Hill, Marcel N. Tutt
  • Patent number: 9781120
    Abstract: A system on chip comprises a responder unit comprising a set of responder elements and an access control unit associated with an authorization list and the responder unit. An entry of the authorization list defines a set of access requirements in relation to an address space identifying at least part of the responder unit. The access control unit is arranged to: receive a request for access to a target responder element among the responder elements of the responder unit, determine the corresponding set of access requirements for the received access request from the authorization list, and evaluate the request for access with respect to the determined set of access requirements and generate a first request evaluation result.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: October 3, 2017
    Assignee: NXP USA, Inc.
    Inventors: Michael Rohleder, Gary Hay, Thomas Luedeke, Stephan Mueller
  • Patent number: 9780973
    Abstract: A receiver circuit for estimating a state of an uplink channel between a wireless communication unit and a base station in a wireless communication system computes a conditioned Channel Impulse Response (CIR), the amount of conditioning being based on the noise present in the channel. A CIR and a Noise Variance are estimated from a Sounding Reference Signal received from the wireless communication unit. The estimated CIR is conditioned by comparing it with an adaptive threshold value selected from a look up table that lists threshold values against Noise Variance values. The threshold value further conditions the CIR to eliminate noise and interference. The conditioned CIR is converted into the frequency domain and used to provide a channel gain estimate which, together with noise estimates, is used to determine a Signal to Interference Noise Ratio (SINR) for the channel.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: October 3, 2017
    Assignee: NXP USA, INC.
    Inventors: Saurabh Mishra, Ankush Jain
  • Patent number: 9779807
    Abstract: A memory cell includes a single bi-directional resistive memory element (BRME) having a first terminal directly connected to a first power rail and a second terminal coupled to an internal node; and a first transistor having a control electrode coupled to the internal node, and a first current electrode coupled to a first bitline, and a second current electrode coupled to one of a group consisting of: a read wordline and the first power rail.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: October 3, 2017
    Assignee: NXP USA, Inc.
    Inventors: Perry H. Pelley, Frank K. Baker, Jr.
  • Patent number: 9780731
    Abstract: A high frequency amplifier includes a high frequency amplifier transistor integrated in a first die of a first semiconductor technology and a matching circuit. The high frequency amplifier transistor has an input terminal, an output terminal and a reference terminal. The reference terminal is coupled to a reference potential. The matching circuit includes at least a first inductive bondwire, a second inductive bondwire and a capacitive element arranged in series with said inductive bondwires. The capacitive element is integrated in a second die of a second semiconductor technology different from the first semiconductor technology. The second semiconductor technology includes an isolating substrate for conductively isolating the capacitive element from a support attached at a first side to the second die. The capacitive element includes a first plate electrically coupled to a first bondpad of the second die and a second plate electrically coupled to a second bondpad of the second die.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: October 3, 2017
    Assignee: NXP USA, INC.
    Inventors: Youri Volokhine, Basim Noori
  • Patent number: 9781138
    Abstract: A device for providing a security breach indicative audio alert. The device includes: a security monitor adapted to detect a security breach in device and a loudspeaker, the device wherein including a secure audio alert generating hardware, adapted to participate, in response to the detection of the security breach, in a generation of a security breach indicative audio alert. The secure audio alert generating hardware is connected to an audio mixer that is adapted to mix the security breach indicative audio alert signal with audio signals generated by a software controlled audio source to provide a mixed signal. The audio mixer is further adapted to provide the mixed signal to the loudspeaker that reproduces the mixed signal as sound.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: October 3, 2017
    Assignee: NXP USA, Inc.
    Inventors: Roman Mostinski, Asaf Ashkenazi
  • Patent number: 9780558
    Abstract: Semiconductor devices and related electrostatic discharge (ESD) protection methods are provided. An exemplary semiconductor device includes an interface for a signal and a multi-triggered protection arrangement coupled between the interface and a reference node to initiate discharge of the signal between the interface and the reference node based on any one of a plurality of different characteristics of the signal. Discharge of the signal at the interface is initiated based on a first characteristic of the signal, and thereafter, the discharge of the signal at the interface is maintained based on another characteristic of the signal.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: October 3, 2017
    Assignee: NXP USA, INC.
    Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Mazhar Ul Hoque