Abstract: A method for making an electronic component package from an encapsulated panel. The encapsulated panel includes two packaging substrate assembles including electronic components. Access sides of the electronic components face outward from the encapsulated panel. Standoffs separate the packaging substrate assemblies from each other.
Abstract: A system in a package (SIP) has a first die with a first internal voltage level, first die-to-die output circuitry, first die-to-die input circuitry, and first internal logic and a second die with a second internal voltage level, second die-to-die output circuitry, second die-to-die input circuitry, and second internal logic. A first signal is provided to the second internal logic via the first die-to-die output circuitry and the second die-to-die input circuitry, wherein each of the first die-to-die output circuitry and second die-to-die input circuitry selectively level shift the first signal based on the first and second internal voltage levels. A second signal is provided to the first internal logic via the second die-to-die output circuitry and the first die-to-die input circuitry, wherein each of the second die-to-die output circuitry and first die-to-die input circuitry selectively level shift the second signal based on the first and second internal voltage levels.
Abstract: There is disclosed a media player comprising a playing unit being arranged to play at least one media element, and a processing unit being arranged to identify at least one data element in said media element, to extract said data element from the media element, and to make said data element available to an external NFC device. Furthermore, there is disclosed a corresponding method for playing media, a corresponding computer program, and a corresponding article of manufacture.
Abstract: According to an aspect of the invention a system for commissioning devices is provided, which system comprises: a first device and a second device; an RFID tag comprised in the first device; a host processor comprised in the first device; wherein the second device is arranged to generate an electromagnetic field; wherein the RFID tag is arranged to detect the electromagnetic field and to wake up the host processor upon detecting said electromagnetic field in order for the second device to communicate with the host processor. Furthermore, a corresponding method for commissioning devices is provided. Since the RFID tag comprised in the first device is arranged to wake up the host processor, an end-user does not have to switch on the first device manually. Therefore, the user interaction is simplified. Furthermore, there is no need for a separate power button on the first device. The latter reduces cost and simplifies the design of the first device.
Type:
Grant
Filed:
September 19, 2012
Date of Patent:
September 12, 2017
Assignee:
NXP B.V.
Inventors:
Ewout Brandsma, Maarten Christiaan Pennings, Aly Aamer Syed, Timo van Roermund, Ruud Hendricksen, Oswald Moonen
Abstract: Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method includes producing a molded panel containing a sidewall substrate. The molded panel is singulated to produce a Fan-Out Wafer Level Package core including a molded body having a fan-out region in which the sidewall substrate is embedded. A side connect trace is printed or otherwise formed on a sidewall of the Fan-Out Wafer Level Package core and extends at least partially across the embedded sidewall substrate.
Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.
Type:
Grant
Filed:
November 16, 2015
Date of Patent:
September 12, 2017
Assignee:
NXP USA, INC.
Inventors:
Hussain H. Ladhani, Gerard J. Bouisse, Jeffrey K. Jones
Abstract: A micro-electromechanical systems (MEMS) transducer (100, 700) is adapted to use lateral axis vibration to generate non-planar oscillations in a pair of teeter-totter sense mass structures (120/140, 720/730) in response to rotational movement of the transducer about the rotation axis (170, 770) with sense electrodes connected to add pickups (e.g., 102/107, 802/807) diagonally from the pair of sense mass structures to cancel out signals associated with rotation vibration.
Type:
Grant
Filed:
January 31, 2012
Date of Patent:
September 12, 2017
Assignee:
NXP USA, Inc.
Inventors:
Heinz Loreck, Keith L. Kraver, Gary G. Li, Yizhen Lin
Abstract: A communication device is disclosed. The communication device includes a receiver, a transmitter, a memory, a sensor to measure antenna detuning, a plurality of receiver configurations stored in the memory. Each of the plurality of receiver configurations include parameter-value pairs and a control unit, coupled to the sensor and the receiver, to select a receiver configuration from the plurality of receiver configurations based on an output of the sensor. The control unit is configured to alter a processing behavior of the receiver by altering values of receiver control parameters according to the parameter-value pairs.
Abstract: A semiconductor wafer (100) having a regular pattern of predetermined separation lanes (102) is provided, wherein the predetermined separation lanes (102) are configured in such a way that the semiconductor wafer is singularizable along the regular pattern.
Type:
Grant
Filed:
May 17, 2012
Date of Patent:
September 5, 2017
Assignee:
NXP B.V.
Inventors:
Florian Schmitt, Heimo Scheucher, Michael Ziesmann
Abstract: A rail-to-rail comparator circuit includes NMOS and PMOS differential input stages with associated loads that are coupled to a shared-load stage. The shared-load stage is coupled to an output stage that includes two active devices. By sharing the load stage between the two input stages, the comparator has a relatively small circuit area, low power draw, and low propagation delay with rail-to-rail input common-mode voltage range.
Type:
Grant
Filed:
September 4, 2016
Date of Patent:
September 5, 2017
Assignee:
NXP USA, INC.
Inventors:
Hao Zhi, Jie Jin, Yang Wang, Jianzhou Wu
Abstract: A data processing system has a system bus, an analog-to-digital converter (ADC), a signal processor, a memory, compression and packing units, and a debug unit. The ADC samples a baseband signal, and provides a digitized signal representative of the baseband signal the system bus. The signal processing block converts the digitized signal to a processed signal in the frequency domain. The memory is coupled to the system bus and is for storing the processed signal. The compression unit is coupled to the system bus and is for capturing the processed signal and compressing the processed signal to produce a compressed signal. The packing unit is coupled to the compression unit and is for packing the compressed signal to produce a packed signal. The debug unit is coupled to the packing unit and is for converting the compressed and packed signal to a diagnostic message. The disclosed data processing system and method provides diagnostic messages in near real-time.
Abstract: A multi-bit flip-flop has first and second one-bit flip-flops. The multi-bit flip-flop employs inter-cell clock switch (CSW) sharing in which the first and second one-bit flip-flops share at least one clock switch. The multi-bit flip-flop may also employ intra-cell CSW sharing in which at least one of the first and second one-bit flip-flops shares at least one clock switch. The inter-cell CSW sharing enables implementation of multi-bit flip-flops with fewer clock switches and possibly fewer data devices, while reducing power consumption, including state retention power gating power reduction.
Abstract: A voltage metering module for metering a voltage signal at least one analogue to digital converter (ADC) component arranged to receive at an input thereof a voltage signal and to generate a digital signal representative of the received voltage signal. The at least one ADC component includes at least one sampling network controllable to sample the received voltage signal for conversion to a digital signal representative of the received voltage signal and at least one compensation network operably coupled in parallel with the sampling network and controllable to sample the received voltage signal such that an input current of the compensation network at least partially compensates for a component of an input current of the sampling network.
Abstract: A semiconductor device includes a bulk substrate of a first conductivity type, a first semiconductor on insulator (SOI) block in the bulk substrate, a first well of the first conductivity type in the first SOI block, a second well of a second conductivity type in the first SOI block, a first guard ring of the first conductivity type in the first SOI block around at least a portion of a periphery of the first SOI block, and a second guard ring of the second conductivity type in the first SOI block around at least a portion of the periphery of the first SOI block. The first conductivity type is different than the second conductivity type.
Abstract: The embodiments described herein include amplifiers configured for use in radio frequency (RF) applications. In accordance with these embodiments, the amplifiers are implemented to generate a shaped envelope signal, and to apply the shaped envelope signal to transistor gate(s) of the amplifier to provide gate bias modulation. So configured, the shaped envelope signal may facilitate high linearity in the amplifier.
Type:
Grant
Filed:
December 9, 2016
Date of Patent:
September 5, 2017
Assignee:
NXP USA, INC.
Inventors:
Abdulrhman M. S. Ahmed, Joseph Staudinger
Abstract: A method of handling requests between contexts in a processing system includes, in a current context of a source processing system element (PSE): executing a send-and rendezvous instruction that specifies a destination PSE, a queue address in the destination PSE, a set of source registers, and a set of receive registers; and sending a send-and-rendezvous message (SRM) to the destination PSE, wherein the SRM includes an address of the destination PSE, a destination queue address, a source PSE address, and an identifier of the current context in the source PSE.
Abstract: A telecommunication receiver is arranged for receiving related data originating from multiple antennas, which data have different times of arrival due to, for example, different delays. The receiver comprises an input buffer for buffering data, a transform unit for Fourier transforming the data received from the input buffer into transformed data, and an output buffer for buffering the transformed data received from the transform unit. The input buffer is arranged for passing each set of data items to the transform unit when the relevant data item has been received in the input buffer, while the transform unit is arranged for removing redundant parts of the data. In addition, the output buffer is arranged for synchronizing the transformed data. Thus the buffering for delay compensation is carried out in the output buffer.
Abstract: Various circuits and methods are disclosed for generating a regulated voltage. According to an example embodiment, an apparatus includes a voltage regulation circuit including a transistor having a channel between source and drain nodes and a gate for affecting current passing through the channel. The voltage regulation circuit configured and arranged to generate, from a voltage source, a regulated voltage at an output node. The voltage regulation circuit exhibits a transfer function having a pole-frequency that varies in response to changes in the current passed by the transistor. The apparatus also includes a current control circuit connected to the voltage regulation circuit, and configured to adjust current provided to the output node to maintain a relatively constant current through the transistor.
Abstract: An output impedance-matching network for an RF power amplifier die includes a harmonic-prevention circuit that functions like a short circuit at a fundamental frequency of the amplifier and an open circuit at a second harmonic frequency of the amplifier. In certain implementations, the harmonic-prevention circuit has one or more parallel, reactive (LC) legs that resonate at the fundamental frequency and a parallel, reactive (capacitive) leg that causes the harmonic-prevention circuit to resonate at the second harmonic frequency. The harmonic-prevention circuit improves power transfer and efficiency of the RF power amplifier.
Abstract: According to an aspect of the invention, a method for personalizing a secure element for a mobile device is conceived, wherein an application is stored in the secure element and wherein the application is pre-provisioned by loading secure credentials into the application without tying said secure credentials to a specific user of the secure element.