Abstract: A built-in-self-test (BIST) circuit is connected to a processor and a sigma-delta modulator (SDM) and includes an averaging circuit, a reference signal generator, and a comparator. The averaging circuit calculates an average of a sum of a set of bit signals of the SDM output signal over a period of time period, and generates an average SDM signal. The reference signal generator generates a reference SDM signal based on an SDM input signal. The comparator compares the voltage levels of the average SDM and reference SDM signals with a threshold value, and generates a test output signal based on the comparison.

Abstract: A device includes an amplifier having a first path and a second path and a first variable attenuator connected to the first path. The device includes a controller coupled to the first variable attenuator. The controller is configured to determine a magnitude of an input signal to the amplifier. When the magnitude of the input signal is below a threshold, the controller is configured to set an attenuation of the first variable attenuator to a first attenuation value. When the magnitude of the input signal is above the threshold, the controller is configured to set the attenuation of the first variable attenuator to a second attenuation value. The second attenuation value is less than the first attenuation value.

Abstract: A substrate having an edge; a first and second active trace, wherein the first active trace corresponds to a first signal of a differential pair and the second active trace corresponds to a second signal of the differential pair; and a first and second conductive via which are located at different distances from the edge. The first active trace is routed to the first conductive via, and the second active trace is routed around the first conductive via to the second conductive via such that the second active trace is between the first conductive via and the edge. The substrate includes a first plating trace in electrical contact with the first active trace, and a second plating trace in electrical contact with the second active trace, wherein the first and second plating traces are routed to the edge on different metal layers of the substrate.

Abstract: A predistortion method and apparatus are provided which use a DPD actuator (225) to apply a memory polynomial formed with first DPD coefficients to a first input signal x[n], thereby generating a first pre-distorted input signal y[n] which is provided to the non-linear electronic device (253) to produce the output signal, where the memory polynomial may be adaptively modified with a digital predistortion adapter (224) which computes second DPD coefficients u[n] with an iterative fixed-point conjugate gradient method which uses N received digital samples of the first pre-distorted input signal y[n] and a feedback signal z[n] captured from the output signal to process a set of conjugate gradient parameters (u, b, v, r, ?, ?, ?) at each predetermined interval, thereby updating the first DPD coefficients with the second DPD coefficients u[n] generate a second pre-distorted input signal which is provided to the non-linear electronic device.

Abstract: Embodiments of a multi-channel analog to digital converter (ADC) include: a first multiplying digital to analog converter (MDAC) having: first and second switched capacitor circuit paths respectively coupled between first and second input nodes and an input node of a first gain element, a second MDAC having: third and fourth switched capacitor circuit paths respectively coupled between third and fourth input nodes and an input node of a second gain element, a third MDAC having: fifth and sixth switched capacitor circuit paths respectively coupled between a fifth input node and an input node of a third gain element, seventh and eighth switched capacitor circuit paths respectively coupled between a sixth input node and the input node of the third gain element, the fifth input node coupled to an output node of the first gain element, the sixth input node coupled to an output node of the second gain element.

Abstract: Methods, devices and circuits are provided for protecting secure data from being read during a scan chain output. A plurality of scan flip-flops is coupled in a scan chain, and an input circuit is configured to shift input data to the scan flip-flops. A protection circuit is coupled to the scan flip-flops, and the protection circuit configured to detect scan-in of data from the input circuit to a designated one of the scan flip-flops. Scan-out of data from the designated scan flip-flop is enabled in response to detection of a scan-in of data from the input circuit to the designated scan flip-flop. Scan-out of data from the designated scan flip-flop is prevented in response to no detection of scan-in of data from the input circuit to the designated scan flip-flop.

Abstract: An embodiment of a microelectromechanical systems (MEMS) device is provided, which includes a substrate; a proof mass positioned in space above a surface of the substrate, wherein the proof mass is configured to pivot on a rotational axis parallel to the substrate; an anchor structure that includes two or more separated anchors mounted to the surface of the substrate, wherein the anchor structure is aligned with the rotational axis; and an isolation sub-frame structure that surrounds the anchor structure and is flexibly connected to each of the two or more separated anchors of the anchor structure, where the proof mass is flexibly connected to the isolation sub-frame structure.

Abstract: A near field communications (NFC) device is disclosed that intelligently routes NFC data from a NFC device between multiple user interfaces based upon a power level of its internal batteries. The communications device utilizes a communications device user interface to send and/or receive the NFC data from the NFC device when its internal batteries are sufficient to operate the communications device user interface. The communications device begins to route some of this NFC data from being sent and/or received by the communications device user interface to a NFC user interface as its internal batteries deplete. Eventually, all of the NFC data will be sent to and/or received by the NFC user interface as the internal batteries of the communications device become so depleted that they are unable to reliably operate the communications device user interface.

Abstract: In various embodiments, a semiconductor package includes a carrier amplifier connected to a first output of a power divider, and a first output matching network connected to the carrier amplifier and an output combining node. The first output matching network exhibits a phase delay during operation of the carrier amplifier. The semiconductor package includes a phase advance network connected to the first output matching network. The phase advance network is configured to offset at least a portion of the phase delay of the first output matching network. The semiconductor package includes a peaking amplifier connected to a second output of the power divider and the output combining node, and a second output matching network connected to the peaking amplifier.

Abstract: Embodiments of semiconductor devices (e.g., RF devices) include a substrate, an isolation structure, an active device, a lead, and a circuit. The isolation structure is coupled to the substrate, and includes an opening. An active device area is defined by a portion of the substrate surface that is exposed through the opening. The active device is coupled to the substrate surface within the active device area. The circuit is electrically coupled between the active device and the lead. The circuit includes one or more elements positioned outside the active device area (e.g., physically coupled to the isolation structure and/or under the lead). The elements positioned outside the active device area may include elements of an envelope termination circuit and/or an impedance matching circuit. Embodiments also include method of manufacturing such semiconductor devices.

Abstract: An electronic apparatus includes a semiconductor substrate and first and second transistors disposed in the semiconductor substrate. The first transistor includes a channel region and a drain region adjacent the channel region. The second transistor includes a channel region, a false drain region adjacent the channel region, and a drain region electrically coupled to the channel region by a drift region such that the second transistor is configured for operation at a higher voltage level than the first transistor. The respective channel regions of the first and second transistors have a common configuration characteristic.

Abstract: A data processing device and a method for performing second or next stage of an N point Fast Fourier Transform is suggested. The processing device comprises an input operand memory unit and an input buffer comprising a plurality of addressable memory cells arranged in lines and columns. Furthermore, the device comprises a number of radix-P operation units for producing output operands that are buffered in an output buffer. Input operands are read from the input operand memory unit and buffering into the input buffer. The input operands are stored and fetched from the input buffer according to a reordering scheme that allows efficient parallel processing of the operands by the butterflies and the buffering of subsequent input operands.

Abstract: A semiconductor die with backside protection includes an active region and a first polysilicon layer formed on a front side of a semiconductor substrate. A signal net is connected to the first polysilicon layer by way of a metal contact and a conductive wire is formed above the active region. During an invasive attack, when a trench is formed in the substrate and an electrically conductive filling is deposited in the trench, the signal net, the conductive wire, and the first polysilicon shape form a short-circuit, which renders the die dysfunctional and thereby foiling the invasive attack.

Abstract: A tag store system and method for making contactless tags available to end users of tag-related software applications is described. The system and method employs an identifier for a tag ordering interface, which is generated using tag framework data for a contactless tag associated with a tag-related software application. The tag ordering interface allows the contactless tag to be ordered using the tag ordering interface. The identifier is included in the tag-related software application and is used to request for the tag ordering interface from an end user device running the tag-related software application.

Abstract: A semiconductor device is disclosed that comprises a first non-volatile memory cell, a second non-volatile memory cell, an active region between the first and second memory cells, and an electrically conductive contact touching the active region, wherein the contact has a horizontal cross-section that is at least five percent smaller in a first dimension than in a second dimension.

Abstract: A system-on-chip device comprises a core supporting a first virtual machine image and a virtual machine monitoring unit capable of communicating with the first virtual machine image. A shareable resource is also provided as well as a conflict detection unit capable of communicating with the virtual machine monitoring unit and the first virtual machine image. The conflict detection unit is arranged to detect, when in use, an access conflict caused by more than one virtual machine image attempting to access initially the shareable resource. The conflict detection unit is arranged to refer, when in use, the access conflict in response to detection thereof to the virtual machine monitoring unit for resolving of the access conflict, thereby handling the access conflict before the virtual machine monitoring unit.

Abstract: One example discloses an apparatus for synchronization, including: a first wireless device, having a first device profile, a near-field magnetic induction (NFMI) signal input and a wireless signal input; wherein the first wireless device is configured to, receive, through the wireless signal input, a first set of data; optimize the first set of data based on the first device profile; receive, through the NFMI signal input, a second set of data optimized for a second device profile of a second wireless device; and synchronize the first and second sets of optimized data based on a set of common data attributes.

Abstract: A voltage supply circuit for an electronic circuit includes a switch configured to selectively connect a supply input of the electronic circuit with a main supply voltage source. An auxiliary voltage supply unit has an auxiliary voltage output coupled to the supply input of the electronic circuit. The auxiliary voltage supply unit is configured to at least temporarily output an auxiliary voltage to the supply input. The auxiliary voltage has a voltage level lower than a voltage level of a main supply voltage supplied by the main supply voltage source.

Abstract: One example discloses a system for filtering digital certificates within a communications network, comprising: a first set of network-nodes, having a first attribute and a respective first set of digital certificates; a second set of network-nodes, having a second attribute and a respective second set of digital certificates; and a digital certificate authority, having a digital certificate validity list which includes the first and second sets of digital certificates; wherein the certificate authority filters the validity list based on the first attribute and transmits the filtered validity list to the first set of network nodes. Another example discloses a method for filtering digital certificates, comprising: maintaining a digital certificate validity list; identifying a set of network-nodes, having an attribute; filtering the validity list based on the attribute; and transmitting the filtered validity list to the set of network-nodes.

Abstract: Aspects of various embodiments of the present disclosure are directed to applications utilizing voltage sampling. In certain embodiments, a sample and hold circuit is configured to sample voltages that exceed a tolerance voltage of components. The circuit includes a first and a second capacitors. In a first mode, a voltage difference between an input node and a first reference voltage is sampled using the first capacitor. Also in the first mode, a voltage stored by the second capacitor is referenced to a second reference voltage and provided to a first output node. In a second mode, a voltage difference between an input node and a first reference voltage is sampled using the second capacitor. Also in the second mode, a voltage stored by the first capacitor is referenced to the second reference voltage and provided to a second output node.