Abstract: Embodiments of methods and systems for digital circuit scan testing are described. In one embodiment, a method for scan testing a digital circuit involves testing a digital circuit using a scan chain to generate scan data and distributing the scan data over a plurality of scan output terminals using a sample and hold device.

Abstract: The present application relates to a reinforcing structure for reinforcing a stack of layers in a semiconductor component, wherein at least one reinforcing element having at least one integrated anchor-like part, is provided. The basic idea is to reinforce bond pad structures by providing a better mechanical connection between the layers below an advanced underbump metallization (BUMA, UBM) by providing reinforcing elements under the UBM and/or BUMA layer.

Abstract: The disclosure relates to a voltage generator for providing an output voltage in accordance with a received target signal, the voltage generator comprising: a resonant converter configured to receive an input voltage, the resonant converter comprising: a first switch; a second switch connected in series with the first switch between the input voltage and ground (GND); a resonant tank associated with the second switch; an output capacitor coupled to the resonant tank and configured to provide an output voltage; and a rectifier configured to allow charge to flow in a single direction between the resonant tank and the output capacitor; and a controller configured to receive the target signal and to set an operating parameter of the resonant converter in accordance with a difference between an output value which is related to the output voltage and the target signal.

Abstract: Various embodiments relate to an apparatus and associated method for a contactless front-end (CLF) managing a secure element (SE). When the SE receives a low power, a monitoring circuit in the CLF may monitor a power supplied to the SE. Upon detection of an under-voltage condition, the monitoring circuit may cause a management module in the CLF to react to the detected under-voltage condition with an SE management technique. The management module may enact the SE management technique through a separate communications interface connected to the SE. In some embodiments, the CLF may further comprise a register that maintains an under-voltage flag that is triggered when the monitoring circuit detects an under-voltage condition. The management module may reset the under-voltage flag and may use the triggering of the under-voltage flag one or more times to determine whether to react through use of a SE management technique.

Abstract: Capacitance multiplier circuitry provides an increased equivalent capacitance, and may be implemented using a desirably small footprint. As may be implemented in accordance with one or more embodiments, a capacitor provides a first capacitance across first and second plates, and capacitance multiplier circuitry operates with the capacitor to provide a second equivalent capacitance that is a multiple of the first capacitance. The capacitance multiplier circuitry includes a first circuit path having a first resistor between the first plate and a common terminal, and a second circuit path having a switch and a second resistor between the second plate and the common terminal. An amplifier has differential inputs respectively corresponding to the first and second circuit paths and provides the second equivalent capacitance by controlling operation of the switch based upon the differential inputs and the respective resistances provided by the resistors in the first and second circuit paths.

Abstract: A diode comprising a reduced surface field effect trench structure, the reduced surface field effect trench structure comprising at least two trenches formed in a substrate and separated from one another by a joining region of the substrate, the joining region comprising an electrical contact and a layer of p-doped semiconductor material.

Abstract: A radio frequency filter (1) comprises an input impedance adaption section (2) and a tank capacitor section (3). Thereby, the capacity of the input impedance adaption section (2) does not comprise a fixed capacitor, it only comprises switchable capacitors. Further, the tank capacitor section (3) does not comprise a fixed capacitor as well it only comprises switchable capacitors. The capacity of the input impedance adaption section (2) can be tuned independent of the tank capacity, section capacity by means of switchable capacitors. Hence, bandwidth and frequency of the radio frequency filter can be modified independent of each other. The imput impendance adaption section (2) is connected in series between the input and output of the filter (1). The tank capacitor section (3) is shunt connected between the input-output series path of the filter (1) and ground.

Abstract: A semiconductor device and a method of making the same. The semiconductor device includes a semiconductor substrate mounted on a carrier. The semiconductor substrate includes a Schottky diode. The Schottky diode has an anode and a cathode. The semiconductor device also includes one or more bond wires connecting the cathode to a first electrically conductive portion of the carrier. The semiconductor device further includes one or more bond wires connecting the anode to a second electrically conductive portion of the carrier. The first electrically conductive portion of the carrier is electrically isolated from the second electrically conductive portion of the carrier. The first electrically conductive portion of the carrier is configured to provide shielding against electromagnetic interference associated with switching of the anode during operation of the device.

Abstract: Aspects of the present disclosure are directed to single-wire bus communications. In accordance with one or more embodiments, a pull-up current is delimited when a single-wire bus circuit is operated at a dominant level during the transmission of data on the single-wire bus circuit. This approach can be implemented to facilitate power savings, such as in applications involving a master control circuit that transmits signals by driving the single-wire bus circuit between dominant and recessive levels.

Abstract: An electronic counter is provided having a sequence of memory cells and increment logic. Each memory cell of the sequence is non-volatile and supports a one state and a zero state. The one state can also be referred to as a ‘programmed state’, the zero state as an ‘erased state’. The counter is configured to represent at least part of a current counting-state of the counter as a pattern of one and zero states in the memory cells of the sequence of memory cells, and increment logic configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter.

Abstract: A method of determining a fingerprint identification of a cryptographic implementation in a cryptographic system, including: receiving, by the cryptographic system, an input message that is a fingerprint identification message; performing, by the cryptographic system, a keyed cryptographic operation mapping the fingerprint identification message into an output message that includes a fingerprint identification; and outputting the output message.

Abstract: Aspects of the present disclosure are directed to apparatuses and methods involving the detection of signal characteristics. As may be implemented in accordance with one or more embodiments, an apparatus includes a radar or sonar transceiver that transmits signals and receives reflections of the transmitted signals. A data compression circuit determines a compression factor based on characteristics of the signals, such as may relate to a channel over which the signal passes and/or related aspects of an object from which the signals are reflected (e.g., velocity, trajectory and distance). Data representing the signals is compressed as a function of the determined compression factor.

Abstract: An apparatus includes an antenna structure with a core shaped as a toroid that is designed to be worn on a human digit. A first and second contact are located on the core. A conductive path connects the first contact and the second contact and includes a first set of windings that traverse a circumference of the core in a substantially parallel manner; and a second set of windings that traverse the circumference of the core in a substantially parallel manner. The windings are such that, from a vantage point exterior to the core, the first set of windings is substantially perpendicular to the second set of windings.

Abstract: Various embodiments relate to a light emitting diode protection circuit, including: a plurality of diodes connected in series; an input connected to a first diode of the plurality of diodes; an output; a first resistor connected between the plurality of diodes and the output; a transistor with a gate connected to a junction between the first resistor and the plurality of diodes and a source connected to the output; a second resistor connected between the input and drain of the transistor; and a silicon controlled rectifier (SCR) with an anode connected to the input, a base connected to the drain of the transistor, and a cathode connected to the output.

Abstract: It is described a method for operating a transponder (203), the method comprising: receiving, by the transponder, in particular wirelessly, transmitted reader data (205) representing x and sqrt[b]/x, wherein x is an element of a binary Galois field and b is a scalar; processing, by the transponder, the reader data (205) to determine, whether x is a first coordinate of a point on an elliptic curve defined by the elliptic curve equation y2+xy=x3+ax2+b, wherein the elliptic curve is defined over the Galois field such that x and y are elements of the Galois field, wherein y is a second coordinate of the point on the elliptic curve. Further a transponder, a method for operating a reader and a reader are described.

Abstract: Embodiments of methods and systems for digital circuit scan testing are described.

Abstract: Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate (100) to form a buried region (150, 260) therein; forming a halo implant (134) using an impurity of a second type and a shallow implant (132) using an impurity of the first type, said halo implant enveloping the shallow implant in the substrate and being located over said buried region (150, 250); forming, adjacent to the halo implant (134), a further implant (136) using an impurity of the second type for providing a conductive connection to the halo implant; and providing respective connections (170, 160, 270) to the further implant (136), the shallow implant (132) and the buried region (150, 260) allowing the shallow implant, halo implant and buried region to be respectively operable as emitter, base and collector of the vertical bipolar transistor.

Abstract: Power supply is facilitated. In accordance with one or more embodiments, a power regulator circuit includes first and second regulators and a controller for controlling operation of the power regulator circuit in standby and normal operational modes. The first and second regulators respectively provide regulated power at main and standby power levels, the standby power level being lower than the main power level. For the standby mode, the controller operates the second regulator for supplying power to an integrated circuit at the standby power level. For transitioning to the normal mode, the controller turns the first regulator on while continuing to operate the second regulator for supplying power to the integrated circuit during a start-up period. After a start-up period (e.g., when the first regulator is up to full power), the controller operates the first regulator for supplying power for operating the processor in a high-frequency mode.

Abstract: A radar data processing system is disclosed. The system includes a microcontroller and a data receiver-transmitter integrated circuit coupled to the microcontroller. The data receiver-transmitter integrated circuit includes a sensor and a dedicated error indicator pin. The data receiver-transmitter integrated circuit includes an inner safety monitor and the microcontroller includes an outer safety monitor. The inner safety monitor configured to receive and collate sensor data from the plurality of sensors and send, through the dedicated error indicator pin, a function warning signal to the outer safety monitor when the sensor data from the sensor is indicative of a functional irregularity.

Abstract: A method of forming semiconductor devices on a leadframe structure. The leadframe structure comprising an array of leadframe sub-structures each having a semiconductor die arranged thereon. The method comprises; providing electrical connections between terminals of said lead frame sub-structures and said leadframe structure; encapsulating said leadframe structure, said electrical connections and said terminals in an encapsulation layer; performing a first series of parallel cuts extending through the leadframe structure and the encapsulation layer to expose a side portion of said terminals; electro-plating said terminals to form metal side pads; and performing a second series of parallel cuts angled with respect to the first series of parallel cuts, the second series of cuts extending through the lead frame structure and the encapsulation layer to singulate a semiconductor device from the leadframe structure.