Abstract: An FET RF signal detector circuit comprising two unbalanced differential transistor pair circuits is disclosed. A current mirror output circuit is included for generating an output current derived from currents flowing in the differential transistor pair circuits. The first unbalanced differential transistor pair circuit comprises two branches, each with a respective tail, and a first variable resistor between the branch tails. The first unbalanced differential transistor pair circuit connects to a first current source tail arrangement. The second unbalanced differential transistor pair circuit comprises two branches, each with a respective tail, and a second variable resistor between the branch tails. The second unbalanced differential transistor pair circuit connects to a second current source tail arrangement.

Abstract: Embodiments of methods and system for transferring semiconductor devices from a wafer to a carrier structure are described. In one embodiment, a method for transferring semiconductor devices from a wafer to a carrier structure involves positioning a carrier structure with a bond surface extending in a first plane and transferring a semiconductor device from a wafer onto the bond surface of the carrier structure using a plurality of rotatable transfer assemblies. Centers of the rotatable transfer assemblies are positioned in parallel with the first plane.

Abstract: A device includes a near field communication (NFC) circuit (114) that is configured and arranged to communicate data with external devices (102). An internal communication circuit (112) communicates data over a microprocessor bus (110). A secure memory circuit (118) stores an identifier that is unalterable in the secure memory circuit. Logic circuitry (116) performs a secure transaction protocol.

Abstract: Methods for bidirectional communication and bidirectional communication buffers are described. In one embodiment, a method for bidirectional communication using first and second communication buses, which have opposite directions of data transmission, is described. The method for bidirectional communication involves detecting a signal from a first communication bus and buffering the detected signal and transmitting the buffered signal through a second communication bus while blocking data transmission from the second communication bus. Other embodiments are also described.

Abstract: A sigma delta receiver achieves increased stability and noise reduction. The sigma delta receiver includes a first integrator stage, an isolation stage, a second integrator stage, and a quantization stage. The first integrator stage receives an analog radio frequency (RF) signal from an antenna and generates an analog baseband signal based on the analog RF signal. The isolation stage is coupled to an output of the first integrator stage. The isolation stage receives the analog baseband signal from the first integrator stage and amplifies the analog baseband signal. The second integrator stage is coupled to an output of the isolation stage to receive the analog baseband signal. The second integrator stage further amplifies the analog baseband signal. The quantization stage converts the analog baseband signal to a digital signal, and outputs the digital signal.

Abstract: Device for generating a message authentication code for authenticating a message, wherein the message is divided in blocks (M) with a specified block length, the device comprising a generating unit for generating the message authentication code based on a message by using a block cipher algorithm, and an encrypting unit for performing an exclusive disjunction on the last block with a first key (K1, K2) and for performing an exclusive disjunction on the first and/or the last block additionally with a second key (K3, K4) for generating the message authentication code.

Abstract: The master secure element comprises a processor, a memory and a logic unit and at least controls the user input of the handset in order to secure the user authentication based on PIN entry. The PIN code is entered directly into the secure element with no possibility for the host processor to intercept the code or for a malware program to inject the code into the master secure element.

Abstract: A non-volatile memory (50) is disclosed. A second electrode (56) is provided. A first electrode (51) is also provided. A recording layer having a plurality of phase change cells (54) variable in resistance is provided between the first electrode (51) and the second electrode (56). A non-uniform tunnel barrier (540) is provided adjacent each of the recording layer and the first electrode. In use, the first electrode is in electrical communication with the non-uniform tunnel barrier, the first electrode for electrically communicating with the second electrode via the non-uniform tunnel barrier.

Abstract: Embodiments of a latch circuit and a method of operating a latch circuit are described. In one embodiment, a latch circuit includes an input terminal configured to receive an input data signal, a switching unit configured to control application of the input data signal, a first inverter circuit connected to the switching unit, where the first inverter circuit includes a first cross-coupled pair of inverters, and a second inverter circuit connected to the first inverter circuit through the switching unit. The second inverter circuit includes a second cross-coupled pair of inverters and two transistor devices. Each inverter of the second cross-coupled pair of inverters is connected to a voltage rail through a corresponding transistor device. Each of the two transistor devices is connected to a node that is between the switching unit and the first inverter circuit or the second inverter circuit. Other embodiments are also described.

Abstract: It is an object of the invention to provide a memory architecture that can handle data interleaving efficiently. This and other objects are achieved by the system according to the invention. The data handling system, is configured for receiving at an input a plurality of commands. The system comprises: a plurality of memory banks; a distributor connected to the input and having a plurality of distributor outputs. Each specific one of the plurality of memory banks (106) is connected to a specific one of the plurality of distributor outputs. The distributor comprises a permutator for designating for each specific command a specific distributor output. The distributor distributes the specific command to the specific designated distributor output. The permutator has a control input and the designating is reconfigurable under the control of reconfiguration data received at the control input.

Abstract: A latch circuit is based on a master-slave cross-coupled inverter pair configuration. The inverters of the slave circuit are coupled to a high voltage rail and a low voltage rail, wherein for each of the two inverters of the slave circuit inverter pair, the coupling to one of the voltage rails is through a resistive element. This circuit design avoids the need for an internal clock-buffer and enables single phase clocking, and therefore does not need internal clock signal inversion. The circuit can be implemented with low power, with no dynamic power consumption for redundant transitions when the input and the output data signal is same.

Abstract: Embodiments of a method and system are disclosed. One embodiment of an integrated circuit device is disclosed. The integrated circuit device includes first and second processor cores configured to perform a respective first and second set of functional processing. The integrated circuit device also includes a core-specific process state monitor associated with the first processor core, a core-specific process state monitor associated with the second processor core, a core-specific aging monitor associated with the first processor core, a core-specific aging monitor associated with the second processor core, a power management unit, a clock generation unit, and a control system configured to individually control operating points of the first and second processor cores and workload in response to feedback from the core-specific process state monitors and from the core-specific aging monitors.

Abstract: An integrated circuit comprises: a first processing stage comprising processing logic for performing a processing operation on an input signal to generate an output signal, wherein the input signal corresponds to an output signal of a previous processing stage; a first sampling element adapted to sample a first value of said output signal synchronously with a clock signal; a second sampling element adapted to sample a second value of said output signal synchronously with a first delayed clock signal; and a first delayed clock signal generator, adapted to selectively generate said first delayed clock signal in response to a control signal generated in said previous processing stage.

Abstract: A loudspeaker drive circuit comprises an input for receiving an audio signal and a signal processor for processing the audio signal before application to the loudspeaker. The signal processor processes the audio signal to derive a loudspeaker drive signal which results in the loudspeaker membrane reaching its maximum displacement in both directions of diaphragm displacement.

Abstract: A method of performing a cryptographic operation using a cryptographic implementation in a cryptographic system, including: receiving, by the cryptographic system, an identifying string value; receiving, by the cryptographic system, an input message; performing, by the cryptographic system, a keyed cryptographic operation mapping the input message into an output message wherein the output message is the correct result when the identifying string value equals a binding string value.

Abstract: Embodiments of digital-to-analog converters (DACs), methods for operating a DAC, and transceiver circuits are described. In one embodiment, a DAC includes an input terminal configured to receive a digital signal, a converter circuit configured to convert the digital signal into an analog signal using first-order interpolation allowing low electromagnetic emissions, and an output terminal configured to output the analog signal. Other embodiments are also described.

Abstract: Using a clock circuit, a clock signal is generated at a base frequency. A frequency adjustment circuit selects, based upon a frequency offset value, a particular frequency adjustment value from a plurality of frequency adjustment values. An adjusted clock signal is provided that has a frequency corresponding to the base frequency as modified by the particular frequency adjustment value. Wireless communication signals are received at a wireless communication circuit. From the communication signals, a set of received wireless communication pulses are identified that have a pulse repetition frequency that corresponds to the adjusted clock signal. A distance ranging protocol is applied, using a processing circuit, to the identified set of received communication pulses.

Abstract: A low-pass filter comprising: a filter input terminal; a filter output terminal; a filter FET configured to provide a resistance between the filter input terminal and the filter output terminal; a filter capacitor connected between the filter output terminal and a reference terminal; a bias FET configured to provide a bias voltage to the filter FET; a buffer connected between the filter input terminal and the bias FET, the buffer configured to source a bias current for the bias FET; and an offset voltage source configured to contribute to the bias voltage provided to the filter FET.

Abstract: Various exemplary embodiments relate to a wireless communications device and related method and machine-readable storage medium including: at least one antenna; a transmission circuit to transmit data via the at least one antenna and a wireless communications medium according to any of a plurality of modulation schemes; a reception circuit to receive data via the at least one antenna; an application controller to generate a series of messages having a message type and associated with an application; and a message scheduler to provide modulation settings to the transmission circuit for respective messages of the series to be transmitted according to different modulation schemes of the plurality of modulation schemes, wherein modulation schemes are chosen for transmission based on a modulation scheme pattern, whereby a first message is transmitted according to a first modulation scheme and a second message is transmitted according to a second modulation scheme.

Abstract: A method for performing foreign object detection in an inductive wireless power transfer system is disclosed. In the embodiment, the method involves obtaining measurements from a base station of a wireless power transfer system during charging and determining transmitter energy loss in a power transmitter, Ptxloss, using the obtained measurements, wherein the transmitter energy loss, Ptxloss, is a function of at least Vcap and PTx, wherein Vcap is proportional to the voltage amplitude across the capacitor of an LC tank circuit in a power transmitter and PTx is the total power supplied to the power transmitter. The method also involves detecting the presence of a foreign object in response to the estimated transmitter energy loss.