Abstract: A low drop-out voltage regulator, an integrated circuit, a sensor and a method of providing a regulated voltage are provided. The low drop-out voltage regulator comprises a regulated voltage driver for providing the regulated voltage in response to a control voltage, a feedback-loop circuit for generating the control signal such that the regulated voltage driving circuit provides the regulated voltage, and a pull-up circuit for pulling up the regulated voltage to a supply voltage when a difference between the supply voltage and the control voltage is smaller than a predetermined threshold value. In the feedback-loop circuit a first feedback voltage or a second feedback voltage is generated, respectively, on basis of a first ratio and a second ratio between the feedback voltage and the regulated voltage. The second feedback voltage is generated instead of the first feedback voltage when the regulated voltage is pulled-up to the supply voltage.

Abstract: A gate drive circuit includes a first switch and a first capacitor. A first terminal of the first capacitor is electrically coupled to the first switch. The first switch is electrically coupled between the first terminal and a voltage supply of the power transistor. A second terminal of the first capacitor is electrically coupled to the reference potential. The gate drive circuit further includes a first voltage limiter in parallel with the first capacitor. The first voltage limiter limits a voltage across the first capacitor to a first predetermined voltage. The gate drive circuit further includes a second capacitor, a pre-charging circuit arranged between the first terminal of the first capacitor and a first terminal of the second capacitor. The gate drive circuit further includes a third capacitor with a first terminal electrically coupled to a second terminal of the second capacitor and a second terminal electrically coupled to a gate terminal of the power transistor.

Abstract: A power factor corrector raises power factor at low loads or high mains voltages by modifying the switch timing or the current received by the power converter. It achieves this by increasing the switch-on time of a control switch during the falling time so that the majority of the switch-on time during a mains period occurs during the falling time, to thereby control the current received by the converter to compensate for current received by the intermediate filter. Some embodiments may employ a feedback system to produce one or more error signals that modify the control signal used to control the operation of the converter. Various embodiments may also include additional stages that limit the compensation range of the error signal.

Abstract: A method for testing a plurality of pressure sensors on a device wafer includes placing a diaphragm of one of the pressure sensors on the device wafer in proximity to a nozzle of a test system. A pneumatic pressure stimulus is applied to the diaphragm via an outlet of the nozzle and a cavity pressure is measured within a cavity associated with the pressure sensor in response to application of the pneumatic pressure stimulus. The pneumatic pressure stimulus within the cavity corresponds to the pressure applied to the diaphragm. Methodology is executed to test the strength and/or stiffness of the diaphragm. Additionally, the methodology and test system can be utilized to determine an individual calibration factor for each pressure sensor on the device wafer.

Abstract: An embodiment of a packaged radio frequency (RF) amplifier device includes a transistor and an inverse class-F circuit configured to harmonically terminate the device. The transistor has a control terminal and first and second current carrying terminals. The control terminal is coupled to an input lead of the device, and the first current carrying terminal is coupled to a voltage reference. The inverse class-F circuit is coupled between the second current carrying terminal and an output lead. The inverse class-F circuit includes a shunt circuit coupled between a cold point node and the voltage reference, where the cold point node corresponds to a second harmonic frequency cold point for the device. The shunt circuit adds a shunt negative susceptance at a fundamental frequency F0 to the inverse class-F circuit.

Abstract: Various embodiments relate to a method of generating tokens for use in modular exponentiation and a related device and non-transitory machine readable storage medium, including: generating a public token, ?, based on an identifier associated with another device; generating a private token, L, as a modular exponentiation of the public token, ?, using a private exponent, d, and modulus, N, from a cryptographic key; and communicating the private token, L, to the other device.

Abstract: A system on chip, SoC, comprising two or more data sources, a memory unit, a memory control unit, and a processing unit. Each of the data sources is capable of providing a data stream. The memory control unit is arranged to maintain, for each of the data streams, a buffer in the memory unit and to route the respective data stream to the processing unit via the respective buffer. Each of the buffers has buffer characteristics which are variable and which comprise at least the amount of free memory of the respective buffer. The memory control unit is arranged to allocate and de-allocate memory regions to and from each of the buffers in dependence of the buffer characteristics of the respective buffer, thereby allowing for re-allocation of memory of the memory unit among the buffers. A method of operating a system on chip is also described.

Abstract: A transistor arrangement is disclosed. The transistor arrangement includes at least first and second sets of sense cells and at least one set of main cells. Each set of sense cells shares drain and gate connections with an associated set of main cells, with a different ratio of number of sense cells to associated main cells for the first set as for the second set.

Abstract: A tape-and-reel system for processing components is disclosed. In the embodiment, the tape-and-reel system includes a first carrier tape reel for holding unloaded carrier tape, a component loading system for loading components into pockets of the unloaded carrier tape, an air-guided cover tape feeder through which cover tape travels, an alignment tool for guiding the cover tape into alignment with the loaded carrier tape and adhering the cover tape to the loaded carrier tape to secure the components into the loaded carrier tape, and a second carrier tape reel for holding the loaded carrier tape.

Abstract: Current sensing circuitry for sensing a current through a load comprises an adaptive-resistance sensor component arranged to be operably coupled in series with the load, and control logic for controlling a resistance of the adaptive-resistance sensor component. The control logic is arranged to receive a signal representative of a voltage across the adaptive-resistance sensor component, compare the received signal to a reference value that is representative of a determined voltage, and in response to the comparison control the resistance of the adaptive-resistance sensor component, such that the voltage across the adaptive-resistance sensor component substantially tracks the determined voltage value.

Abstract: An request controller for controlling requests of a processing unit. The request controller may include an request controller input for receiving an request and an request processing unit connected to the request controller input. The request may request to switch a context of said processing unit or to switch the processing unit from a current an operation to another operation. The request processing unit may decide on the request based on a decision criterion. An request controller output may be connected to the request processing unit, for outputting information about at least granted request. The request processing unit may include a control logic unit including: a state input for receiving information about a current state of a system including the processing unit; and a request input for receiving information about a received request.

Abstract: Apparatuses and methods concerning regulation of load currents are disclosed. As an example, one apparatus includes a first clock generation circuit configured to generate a first clock signal with a frequency spectrum having a first frequency range. A second clock generation circuit is configured to produce a second clock signal by spreading the frequency spectrum of the first clock signal to have a second frequency range that is wider than the first frequency range. The second clock signal has a frequency spectrum extending outside of the frequency range. The apparatus includes a third circuit configured to regulate a voltage at a supply node as a function of the second clock signal. A current regulation circuit is configured to regulate current in a circuit path, from the supply node and passing through a load circuit coupled to the current regulator, as a function of the first clock signal.

Abstract: A current limiter for Class-D amplifiers measures and stores a position of an over-current event. By comparing the stored position, output signals can be selectively inverted. As a result, the Class-D amplifier remains in a defined modulation scheme even during period of current limiting.

Abstract: A controller device can control the time of a slave sub-system in a chain in a base station system. The controller device comprises a slave transceiver for receiving/transmitting from/to a master sub-system, and a synchronization device for synchronizing a clock of the slave transceiver to a clock of the master sub-system based on the received signal received from the master sub-system. The synchronization circuitry comprises a clock input port for receiving an external clock signal from an external clock generator. At a received signal input port the received signal can be received from the master transceiver. A tracking loop couples the received signal input and the second phase input to a control input of a controllable PLL, for providing a negative feedback which controls a phase and/or frequency of the feedback signal to counter the phase and or frequency error between the external clock signal and the received signal.

Abstract: Aspects of the present disclosure are directed to methods, apparatuses and systems involving a multi junction semiconductor circuit. According to an example embodiment, an apparatus includes a multi junction semiconductor circuit including a first current path and a second current path, each current path having respective first and second common voltage nodes to provide an output that is proportional to absolute temperature. The first current path includes a first p-n junction exhibiting a first current density. The second current path includes a second p-n junction exhibiting a second current density that is proportionally different than the first current density, and a resistor connected between the second p-n junction and the second common voltage node. Further, the apparatus includes a current-tap path connected to a node between the resistor and the second p-n junction, the current-tap path diverts a portion of current that flows through the resistor away from the second p-n junction.

Abstract: A receiver component and a method for enhancing a detection range of a time synchronization process in a receiver utilize multiple cross-correlations of a received signal with a known preamble sequence. The results of the multiple cross-correlations are divided into delay segments. The delay segments of one of the multiple cross-correlations are compared with the delay segments of another of the multiple cross-correlations to determine delay of the delay segments of the one of the multiple cross-correlation results.

Abstract: A method of wireless communication, with a circuit that includes a radio frequency identification (RFID) reader, can be carried out using a circuit that is configured and arranged to communicate with RFID cards that use load modulation of an RF carrier provided by the RFID reader. A presence of the radio frequency (RF) carrier is detected on an antenna. A local clock signal is generated. A difference between the local clock signal and the RF carrier is detected. In response to the detected difference, the frequency of the local clock signal is modified to reduce the detected difference. Load modulation of the RF carrier is mimicked by modulating the local clock signal to encode data; and driving the antenna with the modulated local clock signal.

Abstract: One example discloses a transmission line interconnect, comprising: an antenna coupling surface; a transmission line coupling surface; and a dielectric molding compound electromagnetically coupling the antenna coupling surface to the transmission line coupling surface. Another example discloses a method of manufacture, for a transmission line interconnect, comprising: forming a dielectric molding compound; defining an antenna coupling surface on the dielectric molding compound; and defining a transmission line coupling surface on the dielectric molding compound whereby millimeter wave frequencies received at the antenna coupling surface are electromagnetically coupled to the transmission line coupling surface.

Abstract: The invention relates to a computer implemented method of interruption of meta language program code (10) execution on a computer having a micro controller (1) executing a native code (3) execution with a virtual machine (5) executing a meta language program code (10), where an address controller (15) controls the interruption of the meta language program code (10).

Abstract: A circuit, comprising a semiconductor device with one or more field gate terminals for controlling the electric field in a drift region of the semiconductor device; and a feedback circuit configured to dynamically control a bias voltage or voltages applied to the field gate terminal or terminals, with different control voltages used for different semiconductor device characteristics in real-time in response to a time-varying signal at a further node in the circuit.