Patents Assigned to NXP
  • INTEGRATED CIRCUITS SEPARATED BY THROUGH-WAFER TRENCH ISOLATION
    Publication number: 20140151844
    Abstract: An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Applicant: NXP B.V.
    Inventors: Peter Gerard STEENEKEN, Roel DAAMEN, Gerard KOOPS, Jan SONSKY, Evelyne GRIDELET, Coenraad Cornelis TAK
  • POWER STAGE
    Publication number: 20140152353
    Abstract: A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.
    Type: Application
    Filed: February 4, 2014
    Publication date: June 5, 2014
    Applicant: NXP B.V.
    Inventors: Mustafa Acar, Katarzyna Nowak
  • Collapsed mode capacitive sensor
    Patent number: 8742517
    Abstract: A capacitive sensor is configured for collapsed mode, e.g. for measuring sound or pressure, wherein the moveable element is partitioned into smaller sections. The capacitive sensor provides increased signal to noise ratio.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: June 3, 2014
    Assignee: NXP, B.V.
    Inventors: Geert Langereis, Twan Van Lippen, Reinout Woltjer
  • pH sensor and manufacturing method
    Patent number: 8742470
    Abstract: Disclosed is a pH sensor comprising a carrier (10) comprising a plurality of conductive tracks and an exposed conductive area (40) defining a reference electrode connected to one of said conductive tracks; a sensing device (30) mounted on the carrier and connected at least one other of said conductive tracks; an encapsulation (20) covering the carrier, said encapsulation comprising a first cavity (22) exposing a surface (32) of the sensing device and a second cavity (24) exposing the exposed conductive area, said second cavity comprising a reference electrode material (42) and an ion reservoir material (44) sharing at least one ion type with said reference electrode material, the reference electrode material being sandwiched between the exposed conductive area and the ion reservoir material. A method of manufacturing such a pH sensor is also disclosed.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: June 3, 2014
    Assignee: NXP, B.V.
    Inventors: Matthias Merz, Coenraad Cornelis Tak, Romano Hoofman
  • Location-based tracking
    Patent number: 8742908
    Abstract: Object tracking is facilitated. In accordance with one or more embodiments, an object tracking apparatus (200) includes a proximate-range circuit (212), a positioning circuit (214) and a communications circuit (216). The proximate-range circuit wirelessly verifies the identity and presence of at least one proximate-range communications device (220), and the positioning circuit determines positioning information of the object tracking apparatus. The communications circuit receives outputs from the proximate-range circuit and positioning circuit respectively regarding the verification and positioning information, and wirelessly communicates data to a remote communications station based upon the received outputs (140).
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: June 3, 2014
    Assignee: NXP, B.V.
    Inventor: Cedric Boudy
  • MOSFET with temperature sense facility
    Patent number: 8742825
    Abstract: A transistor (1) has a FET (2) and a temperature sensing diode (4) integrated within it. Gate drive circuit (12) is arranged to switch off FET (2) and in this case biasing circuit (14) drives a constant current through the diode (4). The voltage across the diode (4) is measured by voltage sensor (15) which provides a measure of the temperature of the FET.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: June 3, 2014
    Assignee: NXP B.V.
    Inventors: Keith Heppenstall, Adam Brown, Adrian Koh, Ian Kennedy
  • STARTUP CONTROL CIRCUIT IN VOLTAGE REGULATORS AND RELATED CIRCUITS
    Publication number: 20140145695
    Abstract: Aspects of the present disclosure are directed towards apparatus useful for controlling low drop out linear regulators during startup. A voltage regulator device can generate a regulated output voltage from an input voltage and in response to a reference voltage that has, during a startup period, a delayed ramp up relative to a corresponding ramp up of the input voltage. An error circuit generates an error signal in response to a comparison between the output voltage and the reference voltage. An output circuit includes a power transistor that is activated in response to the error signal. A startup control circuit can override, during the startup period for the voltage regulator device, the error signal and thereby counteract activation of the power transistor.
    Type: Application
    Filed: November 26, 2012
    Publication date: May 29, 2014
    Applicant: NXP B.V.
    Inventor: NXP B.V.
  • MIM-CAPACITOR AND METHOD OF MANUFACTURING SAME
    Publication number: 20140145297
    Abstract: An integrated circuit includes a support, at least three metal layers above the support, the metal layers having a top metal layer with a top plate and a bottom metal layer with a bottom plate, dielectric material between the top and bottom plates to form a capacitor, and plural oxide layers above the support, such oxide layers including a top oxide layer, each oxide layer respectively covering a corresponding metal layer. The top oxide layer covers the top metal layer and has an opening exposing at least part of the top plate. A method of forming the integrated circuit by providing a support with metal and oxide layers, including a bottom plate, forming a cavity exposing the bottom plate, filling the cavity with dielectric, applying a further metal layer having a top plate and a further oxide layer, and forming an opening to expose the top plate.
    Type: Application
    Filed: November 28, 2012
    Publication date: May 29, 2014
    Applicant: NXP B.V.
    Inventors: Roel DAAMEN, Gerhard KOOPS, Peter Gerard STEENEKEN
  • CASCODED SEMICONDUCTOR DEVICES
    Publication number: 20140146428
    Abstract: The invention provides a cascode transistor circuit with a main power transistor and a cascode MOSFET formed as an integrated circuit, packaged to form the cascode transistor circuit. A control and protection circuit is integrated into the integrated circuit together and a storage capacitor provides an energy source to drive the control and protection circuit. A charging circuit is also integrated into the integrated circuit for charging the storage capacitor.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 29, 2014
    Applicant: NXP B.V.
    Inventor: Frans PANSIER
  • CASCODED SEMICONDUCTOR DEVICES
    Publication number: 20140145208
    Abstract: A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide FET to provide avalanche protection for the cascode MOSFET transistor.
    Type: Application
    Filed: October 17, 2013
    Publication date: May 29, 2014
    Applicant: NXP B.V.
    Inventors: Matthias ROSE, Jan SONSKY, Philip RUTTER
  • WAFER SEPARATION
    Publication number: 20140145294
    Abstract: A method is provided for separation of a wafer into individual ICs. Channels are formed in the one or more metallization layers on a front-side of the wafer along respective lanes. The lanes are located between the ICs and extend between a front-side of the metallization layers and a backside of the substrate. A backside of the substrate is thinned, and laser pulses are applied via the backside of the substrate to change the crystalline structure of the silicon substrate along the lanes. The plurality of portions in the silicon substrate and the channels are configured to propagate cracks in the silicon substrate along the lanes during expansion of the IC wafer. The channels assist to mitigate propagation of cracks outside of the lanes in the metallization layers during expansion of the IC wafer.
    Type: Application
    Filed: November 28, 2012
    Publication date: May 29, 2014
    Applicant: NXP B.V.
    Inventors: Sascha Moeller, Martin Lapke
  • STANDBY CURRENT REDUCTION THROUGH A SWITCHING ARRANGEMENT WITH MULTIPLE REGULATORS
    Publication number: 20140149764
    Abstract: An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate having a major surface. The integrated circuit also includes a directional light sensor. The directional light sensor includes a plurality of photodetectors located on the major surface. The directional light sensor also includes one or more barriers, wherein each barrier is positioned to shade one or more of the photodetectors from light incident upon the integrated circuit from a respective direction. The directional light sensor is operable to determine a direction of light incident upon the integrated circuit by comparing an output signal of at least two of the photodetectors.
    Type: Application
    Filed: May 6, 2013
    Publication date: May 29, 2014
    Applicant: NXP B.V.
    Inventor: NXP B.V.
  • AMPLIFIER WITH FILTERING
    Publication number: 20140145787
    Abstract: Signals are processed to facilitate the mitigation and/or cancellation of undesirable components within the signal. As consistent with one or more embodiments, input/delay circuits offset the phase of an input signal, as presented to respective amplifiers. The phase offset is used, upon combination of the outputs of the respective amplifiers, to cancel the undesirable components of the signal. Such an approach may, for example, involve phase offset in a digital domain, with correction upon combination of the signals as presented in an analog domain.
    Type: Application
    Filed: November 26, 2012
    Publication date: May 29, 2014
    Applicant: NXP B.V.
    Inventors: Jos Verlinden, Remco van de Beek, Massimo Ciacci
  • CONTROLLING APPLICATION ACCESS TO MOBILE DEVICE FUNCTIONS
    Publication number: 20140149737
    Abstract: There is described a method of controlling application access to predetermined functions of a mobile device. The described method comprises (a) providing a set of keys, each key corresponding to one of the predetermined functions (361, 362, 363, 364), (b) receiving (225) an application from an application provider (220, 221, 222, 223) together with information identifying a set of needed functions, and (c) generating a signed application (301, 302, 309) by signing the received application with each of the keys that correspond to one of the needed functions identified by the received information. There is also described a device for controlling application access and a system for controlling and authenticating application access. Furthermore, there is described a computer program and a computer program product.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 29, 2014
    Applicant: NXP B.V.
    Inventor: Giten Kulkarni
  • PATCH MECHANISM IN EMBEDDED CONTROLLER FOR MEMORY ACCESS
    Publication number: 20140149643
    Abstract: Various exemplary embodiments relate to a patch module connected between a data bus and a ROM memory controller. The patch module may include: at least one patch address register configured to store a ROM address; a patch data register corresponding to each patch address register, each patch data register configured for storing an instruction; an address comparator configured to compare an address received on the data bus with an address stored in each patch address register and output a first signal identifying a matching patch address register and a second signal indicating whether there is a matching address; and a first multiplexer configured to select the patch data register corresponding to the matching patch address register and output the contents of the patch data register to the data bus.
    Type: Application
    Filed: April 19, 2013
    Publication date: May 29, 2014
    Applicant: NXP B.V.
    Inventors: Raymond Devinoy, Nicolas Laine
  • AUDIO SYSTEM
    Publication number: 20140146981
    Abstract: An audio system includes a channel (10) for processing signals. The channel (10) includes a processing module (50) that follows a chain of modules (40) wherein the chain (40) includes a preceding processing module (45). The following processing module (50) is coupled to the preceding processing module (45) in the chain of modules (40) for receiving the output signal (25). The channel (10) further includes a combiner (60). The combiner (60) has two inputs, a first input (65) receives the signal (30) to be processed in the channel (10), and a second input (70) receives a reference signal (75). The combiner (60) further includes an output (80) coupled to an input of the preceding processing module (45) in the chain (40).
    Type: Application
    Filed: November 26, 2013
    Publication date: May 29, 2014
    Applicant: NXP B.V.
    Inventor: Temujin Gautama
  • WIRELESSLY POWERED DEVICES
    Publication number: 20140145513
    Abstract: A circuit for delivering power to a load from a wireless power supply comprises an inductor coil for placing in the electromagnetic field of an inductor coil of a supply and a switchable capacitor bank with capacitors switchable at least between a series and a parallel configuration. The voltage across the capacitor bank is used as a feedback control parameter for controlling the capacitor bank switching. A voltage regulator is used to supply the load with a constant voltage power supply derived from the capacitor bank output.
    Type: Application
    Filed: November 25, 2013
    Publication date: May 29, 2014
    Applicant: NXP B.V.
    Inventors: Ajay Kapoor, Peter Thueringer
  • AMPLIFIER CIRCUIT
    Publication number: 20140145791
    Abstract: A integrated Doherty amplifier circuit comprising a main input terminal, a peak input terminal and an output terminal, a main input conductor and a peak input conductor that are offset from one another in a first direction, the main and peak input conductors extend in a second direction that is perpendicular to the first direction, and wherein an input end of the main input conductor is coupled to the main input terminal and an input end of the peak input conductor is coupled to the peak input terminal, an output conductor that extends in the second direction, an output end of the output conductor is coupled to the output terminal, a main amplifier stage extends in the second direction and has a main stage input and a main stage output, a peak amplifier stage extends in the second direction and has a peak stage input and a peak stage output.
    Type: Application
    Filed: May 3, 2013
    Publication date: May 29, 2014
    Applicant: NXP B.V.
    Inventor: NXP B.V.
  • Vertical MOSFET transistor with a vertical capacitor region
    Patent number: 8735957
    Abstract: Consistent with an example embodiment, there is a package that includes a first voltage terminal, and a second voltage terminal, a first die including a first MOSFET having a drain region electrically connected to the first voltage terminal and further having a source region, A second die is adjacent to the first die, the second die includes a second MOSFET having a drain region electrically connected to the source region of the first MOSFET and having a source region electrically connected to the second voltage terminal. The semiconductor package further includes a vertical capacitor having a first plate electrically connected to the drain region of the first MOSFET and a second plate electrically connected to the source region of the second MOSFET and the second plate is electrically insulated from the first plate by a dielectric material. The capacitor is integrated on the first die or the second die.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: May 27, 2014
    Assignee: NXP B.V.
    Inventor: Phil Rutter
  • Power amplifier circuit and control method
    Patent number: 8736383
    Abstract: A power amplifier circuit uses an output transistor and a cascode transistor. First and second drive circuits apply gate control signals to the two transistors, which rise and fall in synchronism, and this is such that the voltage drop across the cascode transistor is reduced (compared to a constant gate voltage being applied to the output transistor).
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: May 27, 2014
    Assignee: NXP, B.V.
    Inventors: Mustafa Acar, Mark Pieter van der Heijden