Patents Assigned to NXP
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Patent number: 8735198Abstract: One embodiment of the present application includes a multisensor assembly. This assembly has an electromechanical motion sensor member defined with one wafer layer, a first sensor carried with a first one or two or more other wafer layers, and a second sensor carried with a second one of the other wafer layers. The one wafer layer is positioned between the other wafer layers to correspondingly enclose the sensor member within a cavity of the assembly.Type: GrantFiled: December 6, 2005Date of Patent: May 27, 2014Assignee: NXP, B.V.Inventors: Padraig O'Mahony, Frank Caris, Theo Kersjes, Christian Paquet
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Patent number: 8737194Abstract: A receiver system to receive an orthogonal frequency division multiplexing (OFDM) symbol of a certain spectrum efficiency. The receiver system includes a guard interval remover, a memory device, and a pulse shaper. The guard interval remover removes a guard interval from the OFDM symbol received by the receiver. The memory device stores a pulse shaping algorithm. The pulse shaper performs the pulse shaping algorithm to substantially maintain the certain spectrum efficiency in conjunction with the utilization of a Nyquist pulse shape with an excess bandwidth?1.0.Type: GrantFiled: May 1, 2009Date of Patent: May 27, 2014Assignee: NXP, B.V.Inventor: Junling Zhang
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Patent number: 8736387Abstract: A reference circuit, an oscillator architecture that includes the reference circuit and a method for operating the reference circuit are described. In one embodiment, the reference circuit includes a voltage reference generator configured to generate a reference voltage and a current reference generator configured to generate a reference current based on the reference voltage. The current reference generator includes a level shifter circuit configured to generate intermediate voltages based on the reference voltage, a first current reference circuit configured to generate intermediate currents based on the intermediate voltages, where the intermediate currents are correlated to the reference voltage, and a second current reference circuit configured to combine the intermediate currents to generate the reference current. Other embodiments are also described.Type: GrantFiled: July 24, 2012Date of Patent: May 27, 2014Assignee: NXP B.V.Inventors: Kevin Mahooti, Min Ming Tarng, Jason Sharma, Hassan Sharghi, Himanshu Sharma, Amjad Nezami
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Patent number: 8737449Abstract: A frequency hopping receiver circuit has a frequency converter (12) and a hopping control circuit (14) coupled to the frequency converter (12), and configured to control frequency hopping of the received frequency, by controlling changes in frequency shift applied by the frequency converter (12). The frequency change is applied in combination with a temporary reduction in conversion gain of the frequency converter (12) during the change in frequency shift. The frequency converter may contain a mixer (122), a local oscillator circuit (120) and a controllable amplifier (124) coupled between the input of the frequency converter (12) and the mixer (122) or between the mixer (122) and the output of the frequency converter (12), or between the local oscillator circuit (120) and the local oscillator input of the mixer (122).Type: GrantFiled: August 18, 2009Date of Patent: May 27, 2014Assignee: NXP, B.V.Inventors: Jozef Reinerus Maria Bergervoet, Harish Kundur Subramaniyan, Remco Cornelis Herman Van De Beek
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Patent number: 8736473Abstract: A low power, high dynamic range sigma-delta modulator comprises a quantizer followed by a digital integrator for generating an integrated digital signal from a quantized signal. The output of the digital integrator is coupled to a digital-to-analog converter in the feedback loop of the sigma-delta modulator.Type: GrantFiled: August 16, 2010Date of Patent: May 27, 2014Assignee: NXP, B.V.Inventors: Carel Dijkmans, Robert van Veldhoven, Ben Kup, Leon van der Dussen, Harry Neuteboom
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Patent number: 8736395Abstract: The present invention relates to a polar modulation apparatus and method, in which a polar-modulated signal is generated based on separately processed phase modulation (PM) and amplitude modulation (AM) components of an input signal. An amplified polar modulated output signal is generated in accordance with the phase modulation and amplitude modulation components by using a differential power amplifier circuitry(30) and supplying an amplified phase modulation component to a differential input of the differential power amplifier circuitry(30). A bias input of the differential power amplifier circuitry(30) is controlled based on the amplitude modulation component, so as to modulate a common-mode current of the differential power amplifier circuitry(30). Thereby, a new concept of a polar modulator with static DC-DC converter and power and/or efficiency and/or linearity controlled output power amplifier can be achieved.Type: GrantFiled: December 21, 2011Date of Patent: May 27, 2014Assignee: NXP, B.V.Inventors: Mihai A. T Sanduleanu, Ram P. Aditham, Eduard F. Stikvoort
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Publication number: 20140140442Abstract: A circuit and a method are used estimate quality of the output of a wireless receiver. This quality measure is used to control the supply voltage and thereby provide power savings.Type: ApplicationFiled: November 21, 2013Publication date: May 22, 2014Applicant: NXP B.V.Inventor: Jan Hoogerbrugge
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Publication number: 20140143865Abstract: A method of generating identification data for identifying software is disclosed. The method includes executing said software so as to alter one or more addresses of a memory stack reserved in memory for execution of the software. Identification data is then generated for identifying the software based on the one or more altered addresses of the memory stack.Type: ApplicationFiled: October 25, 2013Publication date: May 22, 2014Applicant: NXP B.V.Inventor: Arnaud COLLARD
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Publication number: 20140138855Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) wafer; The wafer has a topside surface and an back-side surface, and a plurality of device die having electrical contacts on the topside surface. The method comprises back-grinding, to a thickness, the back-side surface the wafer. A protective layer of a thickness is molded onto the backside of the wafer. The wafer is mounted onto a sawing foil; along saw lanes of the plurality of device die, the wafer is sawed, the sawing occurring with a blade of a first kerf and to a depth of the thickness of the back-ground wafer. Again, the wafer is sawed along the saw lanes of the plurality of device die, the sawing occurring with a blade of a second kerf, the second kerf narrower than the first kerf, and sawing to a depth of the thickness of the protective layer. The plurality of device die are separated into individual device die.Type: ApplicationFiled: August 14, 2013Publication date: May 22, 2014Applicant: NXP B.V.Inventors: Leonardus Antonius Elisabeth VAN GEMERT, Hartmut BUENNING, Tonny KAMPHUIS, Sascha MOELLER, Christian ZENZ
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Patent number: 8728929Abstract: The invention relates to a method of manufacturing a semiconductor device, the method comprising: i) providing a substrate carrier comprising a substrate layer and a patterned conductive layer, wherein the patterned conductive layer defines contact pads; ii) partially etching the substrate carrier using the patterned conductive layer as a mask defining contact regions in the substrate layer; iii) providing the semiconductor chip; iv) mounting said semiconductor chip with the adhesive layer on the patterned conductive layer such that the semiconductor chip covers at least one of the trenches and part of the contact pads neighboring the respective trench are left uncovered for future wire bonding; v) providing wire bonds between respective terminals of the semiconductor chip and respective contact pads of the substrate carrier; vi) providing a molding compound covering the substrate carrier and the semiconductor chip, and vii) etching the backside (S2) of the substrate carrier to expose the molding compound inType: GrantFiled: December 17, 2010Date of Patent: May 20, 2014Assignee: NXP B.V.Inventors: Jan van Kempen, René Wilhelmus Johannes Maria van den Boomen, Emiel de Bruin
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Patent number: 8729928Abstract: A switching circuit suitable for a low power oscillator circuit includes control and output circuits, the control circuit arranged to control the output circuit, the control circuit having input and output terminals, the output circuit having input and output terminals and control terminals; wherein the input terminal of the control circuit is connected to the input terminal of the output circuit, and the control terminal of the output circuit is connected to the output terminal of the control circuit, the output circuit first switches connected in series and arranged such that in use at least one of the switches is in a low impedance state at any given time, and the control circuit has second switches connected in series and arranged such that in use at least one of the switches is in a low impedance state at any given time.Type: GrantFiled: November 5, 2012Date of Patent: May 20, 2014Assignee: NXP, B.V.Inventor: Timothy Luke Farnsworth
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Patent number: 8729636Abstract: Integrated circuit comprising a substrate carrying at least one transistor comprising an alternating grid (1) of source and drain regions (D, S) separated by a grid (14) of gate regions, e.g. a checkerboard pattern of source and drain regions. The source regions (S) are vertically connected to a first metal layer and the drain regions (D) are vertically connected to a second metal layer. At least one of the first metal layer and the second metal layer comprises a metal grid (30, 40) of a plurality of interconnected metal portions (32, 42) arranged such that said grid comprises a plurality of gaps (34, 44) for connecting respective substrate portions to a further metal layer. Method for manufacturing such an integrated circuit.Type: GrantFiled: July 28, 2009Date of Patent: May 20, 2014Assignee: NXP B.V.Inventor: Jeroen Van Den Boom
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Patent number: 8729679Abstract: Consistent with an example embodiment, there is an integrated circuit device (IC) built on a substrate of a thickness. The IC comprises an active device region of a shape, the active device region having a topside and an underside. Through silicon vias (TSVs) surround the active device region, the TSVs having a depth defined by the substrate thickness. On the underside of and having the shape of the active device region, is an insulating layer. A thin-film conductive shield is on the insulating layer, the conductive shield is in electrical contact with the TSVs.Type: GrantFiled: December 4, 2012Date of Patent: May 20, 2014Assignee: NXP, B.V.Inventor: Chee Keong Phua
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Patent number: 8730698Abstract: A power conversion controller for controlling the operation of a switch in a power conversion circuit, wherein the power conversion controller is configured to operate the switch according to: a variable frequency mode of operation for switching frequencies greater than a minimum threshold value; and a fixed frequency mode of operation at a switching frequency equal to the minimum threshold value.Type: GrantFiled: December 29, 2010Date of Patent: May 20, 2014Assignee: NXP B.V.Inventors: Thomas Antonius Duerbaum, Johann Baptist Daniel Kuebrich, Hans Halberstadt, Frans Pansier, Markus Schmid
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Patent number: 8729973Abstract: A MEMS resonator comprises a resonator body (34), and an anchor (32) which provides a fixed connection between the resonator body (34) and a support body. A resistive heating element (R1,R2) and a feedback control system are used to maintain the resonator body (34) at a constant temperature. A location for thermally coupling the anchor (32) to the resistive heating element (R1,R2) is selected which has a lowest dependency of its temperature on the ambient temperature during the operation of the feedback control.Type: GrantFiled: September 7, 2009Date of Patent: May 20, 2014Assignee: NXP, B.V.Inventors: Jozef Thomas Martinus van Beek, Ronald Vogels
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Patent number: 8730016Abstract: A non-contact communication device is disclosed comprising: an antenna having an input impedance and being for receiving an AC signal having a voltage and a current, a main unit comprising a power-extraction unit and a communication unit and having a main unit impedance, a tuning circuit, and a matching network for matching the input impedance to the main unit impedance, characterized in that the tuning circuit comprises a phase detector for detecting a phase difference between the voltage and the current and is configured to adjust the impedance of the matching network in dependence on the phase difference. Also disclosed is a method for tuning a non-contact communication device.Type: GrantFiled: April 8, 2011Date of Patent: May 20, 2014Assignee: NXP B.V.Inventors: Rachid El Waffaoui, Giuliano Manzi
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Publication number: 20140131899Abstract: The invention refers to method for packaging an integrated circuit (IC) comprising steps of: attaching at least one die on a substrate; attaching bond-wires from the die(s) to package terminal pads; mold or dispense a thermo-degradable material on the substrate, die(s) and bond-wires; mold an encapsulant material; decompose the thermo-degradable materials by temperature treatment.Type: ApplicationFiled: November 11, 2013Publication date: May 15, 2014Applicant: NXP B.V.Inventor: Christian Weinschenk
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Publication number: 20140130346Abstract: Sensor package 1 and a corresponding manufacturing method, wherein the sensor package 1 includes several components like a magneto resistive sensor 40 and electronic components 30, and the orientation of the elements and components is maintained by a moulding body 200 manufactured in a single moulding step.Type: ApplicationFiled: January 15, 2014Publication date: May 15, 2014Applicant: NXP B.V.Inventors: Paulus Martinus Catharina HESEN, Roelf Anco Jacob GROENHUIS, Johannes Wilhelmus Dorotheus BOSCH
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Publication number: 20140132353Abstract: An integrated power amplifier circuit is disclosed. The circuit comprises: first and second amplifiers fabricated on one or more dies, the one or more dies being mounted on a support structure; a first set of one or more connection elements connected to the first amplifier and passing above a portion of the support structure; and a second set of one or more connection elements connected to the second amplifier and passing above a portion of the support structure. The support structure comprises at least one void, at least a portion of the at least one void being positioned directly underneath at least one of the first and second sets of one or more connection elements.Type: ApplicationFiled: November 14, 2013Publication date: May 15, 2014Applicant: NXP B.V.Inventors: Vittorio Cuoco, Josephus Henricus Bartholomeus van der Zanden, Albert Gerardus Wilhelmus Philipus van Zuijlen
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Patent number: 8723592Abstract: Body biasing circuit and methods are implemented in a variety of different instances. One such instance involves placing, a first well of a first body bias island and a second well of a second body bias island in a first bias mode by controlling switches of a body bias switch circuit. The biasing is one of a reverse body bias, a nominal body bias and a forward body bias. The second well is also biased according to one of a reverse body bias, a nominal body bias and a forward body bias. In response to the bias-mode input, the first well of the first body bias island and the second well of the second body bias island are each placed in a second bias mode by controlling switches of the body bias switch circuit. The bias of the first well and second well can be changed.Type: GrantFiled: August 12, 2011Date of Patent: May 13, 2014Assignee: NXP B.V.Inventors: Rinze Meijer, Cas Groot, Gerard Villar Pique