Abstract: A processing system includes an interconnect, a master processing device including processing cores coupled to the interconnect, a hypervisor coupled to the interconnect and configured to allocate the processing cores to one or more virtual machines, domain configuration information including a domain identifier for each of the one or more virtual machines, remote peripheral devices coupled to the interconnect, and a domain access controller coupled to the interconnect and configured to receive the domain identifiers for the remote peripherals directly from the hypervisor through the interconnect.

Abstract: A linear chirp radar system, apparatus and method use a radar control processing unit to control an LFM radar front end which includes a frequency-scanning transmit antenna and a frequency-scanning receive antenna which respectively sweep a transmit and receive energy focus across an angle space with each linear chirp signal, where the radar control processing unit processes digital output signals generated from target return signals received in response to transmitted linear chirp signals and extracts target range-angle information by applying time-frequency analysis processing to the digital output signals to generate a first range-angle map which includes range-biased angle information, and then applying a group delay compensation process to generate a second range-angle map which includes target range-angle information that is generated by selectively adjusting the range-biased angular information in the first range-angle map with an angular adjustment.

Abstract: Embodiments of an apparatus and method are disclosed. In an embodiment, a method of executing block acknowledgement operations in a multi-link communications system comprises transmitting a request for block acknowledgement response from a first multi-link device to a second multi-link device, wherein the request is either in quality of service (QoS) data frames of aggregated-media access control (MAC) protocol data unit (A-MPDU) or a block acknowledgement request, and receiving a block acknowledgment from the second multi-link device by the first multi-link device.

Abstract: A semiconductor device and a method of making the same. The device includes an encapsulant. The device also includes a semiconductor die in the encapsulant. The device further includes electromagnetic radiation transmitting and receiving parts in the encapsulant. The device also includes an intermediate portion having a first surface and a second surface. The first surface is attached to the encapsulant. The device also includes an antenna portion attached to the second surface of the intermediate portion. The antenna portion includes one or more openings for conveying electromagnetic radiation. The intermediate portion includes one or more corresponding openings aligned with the openings of the antenna portion. Each opening of the antenna portion and each corresponding opening of the intermediate portion forms an electrically contiguous passage for conveying the electromagnetic radiation to the electromagnetic radiation transmitting and receiving parts in the encapsulant.

Abstract: A Radio Frequency Identification (RFID) tag is disclosed. The RFID tag includes an antenna to receive a high frequency signal, a capacitor bank coupled with the antenna, a charge pump coupled with the antenna configured to convert the high frequency signal to a direct current (DC) signal, an envelope detector to measure peak voltage of the high frequency signal and a detector to compare an output of the charge pump and an output of the envelope detector. The RFID tag also includes an impedance tuning circuit coupled with the charge pump and the envelope detector configured change a capacitance of the capacitor bank based on an output of the detector and the envelope detector.

Abstract: One example discloses a differential-signal-detection circuit, comprising: an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal; a first comparator coupled to receive the first differential output signal and generate a first comparator output signal; a second comparator coupled to receive the second differential output signal and generate a second comparator output signal; and an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal.

Abstract: Die-substrate assemblies having sinter-bonded backside via structures, and methods for fabricating such die-substrate assemblies, are disclosed. In embodiments, the method includes obtaining an integrated circuit (IC) die having a backside over which a backmetal layer is formed and into which a plated backside via extends. The IC die is attached to an electrically-conductive substrate by: (i) applying sinter precursor material over the backmetal layer and into the plated backside via; (ii) positioning a frontside of the electrically-conductive substrate adjacent the plated backmetal layer and in contact with the sinter precursor material; and (iii) sintering the sinter precursor material to yield a sintered bond layer attaching and electrically coupling the IC die to the frontside of the electrically-conductive substrate through the backmetal layer and through the plated backside via. The sintered bond layer contacts and is metallurgically bonded to the backside via lining.

Abstract: A method for digital-to-analog signal conversion with distributed reconstructive filtering includes receiving a digital code synchronous to a clock signal having a first frequency, determining next states of a plurality of digital-to-analog current elements based on the digital code, combining a plurality of currents to generate an output current, and generating the plurality of currents. Each of the plurality of currents is based on a corresponding control signal of a plurality of control signals. The method includes generating the plurality of control signals based on the next states of the plurality of digital-to-analog current elements. Each of the plurality of control signals selects a first voltage level, a second voltage level, or a transitioning voltage level for use by a corresponding digital-to-analog current element. The transitioning voltage level linearly transitions from the first voltage level to the second voltage level over a predetermined number of periods of the clock signal.

Abstract: Various embodiments relate to a method performed by a station to identify the maximum allowed transmit power spectral density (PSD) of a basic service set (BSS), including: receiving, by the station, a first field from an access point (AP) of the BSS, wherein the first field indicates that the BSS bandwidth is set to M times a unit channel bandwidth; receiving, by the station, a set of second fields from the AP, wherein the set of second fields includes K fields corresponding to K channels and wherein each of the K second fields indicates the maximum allowed transmit PSD for the K channels and the bandwidth of the channel is the unit channel bandwidth; and identifying, by the station, the maximum allowed transmit PSD of the M channels of the BSS bandwidth from the first M consecutive second fields.

Abstract: Digitally controllable elements capable of influencing operation of a power amplifier module are coupled in parallel to a serial data interface. Each digitally controllable element includes address control logic that decodes an address presented on the serial data interface as well as a device specific ID. In response to the decoding, physical registers in different digitally controllable elements are written in an interleaved order according to an interleaved register address map. Banks of registers within the digitally controllable elements may be select to influence or modify operation of the power amplifier module.

Abstract: Digitally controllable elements capable of influencing operation of a power amplifier module are coupled to an interface gateway device using a first serial data interface that communicates using a first serial protocol. The interface gateway device receives serial data on multiple external serial data interfaces that utilize various serial protocols, and converts the various serial protocols to the first serial protocol. Each digitally controllable element includes address control logic that decodes an address presented on the first serial data interface as well as a device specific ID. In response to the decoding, physical registers in different digitally controllable elements are written.

Abstract: Embodiments of a method and an apparatus for wireless communications are disclosed. In an embodiment, a method for wireless communications involves assigning subcarriers of a first access point (AP) and a second AP to a subcarrier set of a virtual AP, generating, by the virtual AP, a packet that includes a signal for a station (STA) and that is transmitted using the subcarrier set, where generating the packet includes: encoding a preamble portion of the packet on the assigned subcarriers included in the subcarrier set, nulling the preamble portion of the packet for unassigned subcarriers of the first AP and the second AP, encoding a subsequent portion of the packet according to a Distributed Multiple-Input Multiple-Output (DMIMO) transmission, and transmitting the packet to the STA.

Abstract: A method of estimating a clock frequency offset in a mobile device relative to a clock frequency of a controller within a UWB network comprises (a) determining, for each of a plurality of anchors, an anchor clock frequency offset relative to the controller clock frequency, (b) broadcasting an anchor data packet from each anchor, the anchor data packet including the respective anchor clock frequency offset, (c) receiving at least one anchor data packet at the mobile device, (d) estimating a mobile device clock frequency offset relative to the anchor clock frequency of the anchor from which the at least one anchor data packet was received, and (e) estimating the clock frequency offset in the mobile device based on the estimated mobile device clock frequency offset and the anchor clock frequency offset included in the at least one received anchor data packet. Furthermore, a TDoA-based localization method and a TDoA-based localization system are described.

Abstract: A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.

Abstract: Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.

Abstract: The internal temperate of a transistor is determined by detecting a voltage though a terminal of an integrated circuit that is also used by an overcurrent detection circuit of the integrated circuit for detecting an overcurrent condition of the system. The overcurrent detection circuit is coupled to a current electrode of the transistor through the terminal of the integrated circuit. A determination of internal temperature is based on a voltage measurement taken from the terminal during an on phase of the transistor. The voltage measurement is converted to a digital value and is used to determine an internal temperature of the transistor.

Abstract: An integrated circuit transformer (150) is formed with a primary winding (91) located in at least a first winding layer having a first thickness, a secondary winding (92) located in at least the first winding layer and having a first center point at the first side of the transformer and two secondary terminals at a second, opposite side of the transformer, and a first center tap feed line (81) located along a symmetry axis of the transformer in an upper metal layer having a second thickness that is at least equivalent to the first thickness of the first winding layer, wherein the first center tap feed line has a direct electrical connection to the first center point in the secondary winding.

Abstract: A first anchor of a first type communicates with a mobile electronic device. A characteristic of the communications between the first anchor of the first type and the mobile electronic device is determined. One or more second anchors each of a second type is selected based on the characteristic of the communications. A respective distance to the mobile electronic is determined based on each of the selected one or more second anchors each of the second type.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a current sensing circuit includes first and second integrated resistors on a semiconductor die, a controllable current source configured to provide a reference current, and a current determination circuit. A resistance value of the second integrated resistor is a factor n larger than a resistance value of the first integrated resistor. A current drawn by a target circuit is configured to flow through the first integrated resistor, and the reference current is configured to flow through the second integrated resistor. The current determination circuit is configured to determine a value of the current drawn by the target circuit based on the value of the reference current when a first voltage at a terminal of the first integrated resistor is approximately equal to a second voltage at a terminal of the second integrated resistor.

Abstract: Embodiments of a method and an apparatus for wireless communications are disclosed. In an embodiment, a method for wireless communications involves operating an Access Point (AP) using feedback subcarrier indices for a bandwidth up to 320 MHz, signaling, by the AP, to a client, a subcarrier location set on which a feedback report is solicited, signaling, by the AP, to a client, a feedback type solicited on the subcarrier location, and indicating, by the client, feedback subcarrier indices for the subcarrier location set via the feedback report solicited by the AP.