Abstract: A no-gel sensor package is disclosed. In one embodiment, the package includes a microelectromechanical system (MEMS) die having a first substrate, which in turn includes a first surface on which is formed a MEMS device. The package also includes a polymer ring with an inner wall extending between first and second oppositely facing surfaces. The first surface of the polymer ring is bonded to the first surface of the first substrate to define a first cavity in which the MEMS device is contained. A molded compound body having a second cavity that is concentric with the first cavity, enables fluid communication between the MEMS device and an environment external to the package.

Abstract: There is described a method of determining a phase value for an NFC card emulating device that enables said NFC card emulating device to communicate in phase with an NFC reader device while utilizing active load modulation, wherein the NFC card emulating device comprises a card antenna and the NFC reader device comprises a reader antenna, the method comprising receiving a reader signal from the NFC reader device at the NFC card emulating device through coupling of the card antenna and the reader antenna, the reader signal comprising a subcarrier modulation; estimating a resonance frequency of a system corresponding to the coupled card antenna and reader antenna based on the received communication signal; and determining the phase value based on the estimated resonance frequency and a set of parameters that represents a predetermined reference system. Furthermore, an NFC card emulating device, an NFC system, and a computer program are described.

Abstract: Embodiments of a method and an apparatus for wireless communications are disclosed. In an embodiment, a method for wireless communications involves, at a first station (STA), transmitting a first Physical Layer Protocol Data Unit (PPDU) that includes a first frame to a second STA, wherein the first frame indicates a first duration of a second PPDU that is transmitted subsequent to the first PPDU by a single STA, wherein a non-Trigger-Based (non-TB) PPDU format is used for the second PPDU, and wherein the first frame solicits a response frame included as part of the second PPDU, and at the first STA, receiving from the second STA, the second PPDU that includes the response frame.

Abstract: A radar system, apparatus, architecture, and method are provided for generating a transmit reference or chirp signal that is applied to a waveform generator having a frequency offset generator and a plurality of single channel modulation mixers configured to generate a plurality of transmit signals having different frequency offsets from the transmit reference signal for encoding and transmission as N radio frequency encoded transmit signals which are reflected from a target and received at a receive antenna as a target return signal that is down-converted to an intermediate frequency signal and converted by a high-speed analog-to-digital converter to a digital signal that is processed by a radar control processing unit which performs fast time processing steps to generate a range spectrum comprising N segments which correspond, respectively, to the N radio frequency encoded transmit signals transmitted over the N transmit antennas.

Abstract: The disclosure relates to a transceiver device, an electronic control unit and an associated method. The transceiver device is suitable for communicating between one or more network protocol controllers and a network bus and comprises: first interface circuitry configured to communicate with the one or more network protocol controllers; second interface circuitry configured to communicate with the one or more network protocol controllers; and selector circuitry configured to switch communication with the one or more network protocol controllers from the first interface circuitry to the second interface circuitry in response to a communication error in data carried on the first interface circuitry.

Abstract: Embodiments of a calibration system for third order intermodulation distortion (IMD3) cancellation and a wireless apparatus are disclosed. In an embodiment, a calibration system for IMD3 cancellation includes a cancellation circuit for IMD3 cancellation between a first transmitter and a second transmitter, and a controller coupled to the cancellation circuit and configured to for each frequency channel of the first transmitter, perform a pre-conditional calibration of the cancellation circuit, after the pre-conditional calibration, determine a phase configuration for the cancellation circuit, and after the phase configuration for the cancellation circuit is determined, determine an attenuation configuration for the cancellation circuit.

Abstract: A device for providing side-channel protection to a data processing circuit is provided and includes a chaotic oscillator and a counter. The data processing circuit has an input for receiving an input signal, a power supply terminal, and an output for providing an output signal. The chaotic oscillator circuit has an input coupled to receive a control signal, and an output coupled to provide an output signal for controlling a voltage level of a power supply voltage of the data processing circuit. The counter has an input coupled to receive a clock signal, and an output coupled to control a variable parameter of the chaotic oscillator in response to the clock signal. In another embodiment, a method is provided providing the side-channel protection to the device.

Abstract: A configurable control loop arrangement for forming a control loop of a DC-DC converter that is configured to generate a control signal to control the DC-DC converter, the configurable control loop arrangement comprising: a digital-to-analog converter; a comparator; a timer configured to provide a timing-signal for controlling one or more of: the comparator in the determination of the comparison signal; the application of the comparison signal to a configurable-event-generation-logic-module; and the operation of the configurable-event-generation-logic-module; wherein the configurable-event-generation-logic-module comprises a flip-flop circuit, and wherein the configurable-event-generation-logic-module, when implemented in the control loop, is configured to provide for generation of the control signal based on the comparison signal, the timing-signal and a selected mode of the flip-flop circuit, and wherein the control signal is for application to one or more switches of the DC-DC converter.

Abstract: A semiconductor device and fabrication method are described for forming a nanosheet transistor device by forming a nanosheet transistor stack (12-18, 25) of alternating Si and SiGe layers which are selectively processed to form metal-containing current terminal or source/drain regions (27, 28) and to form control terminal electrodes (36A-D) which replace the SiGe layers in the nanosheet transistor stack and are positioned between the Si layers which form transistor channel regions in the nanosheet transistor stack to connect the metal source/drain regions, thereby forming a nanosheet transistor device.

Abstract: Embodiments of a method and an apparatus for a quadrature hybrid are disclosed. In an embodiment, a quadrature hybrid includes a first port, a second port, a third port, a fourth port, first, second, and third inductors, first, second, third, and fourth capacitors, and a first variable capacitor tuning network connected between the first port and the fourth port, and a second variable capacitor tuning network connected between the second port and the third port.

Abstract: Various embodiments relate to a method of multi-link operation between two multi-link devices (MLDs) where at least one MLD is a non-simultaneous transmit receive (NSTR) MLD that supports enhanced multi-link radio operation, including: operating, by the NSTR MLD, in a first operating mode, wherein the first operating mode is one of multi-link radio mode or enhanced multi-link radio mode; switching, by the NSTR MLD, between the first operating mode and a second operating mode, wherein the second operating mode is the multi-link radio mode when the first operating mode is the enhanced multi-link radio mode and the second operating mode is the enhanced multi-link radio mode when the first operating mode is the multi-link radio mode; announcing the operation capability by the NSTR MLD; and announcing the operating parameters by the NSTR MLD.

Abstract: A vehicle radar system, apparatus and method use a radar control processing unit generate compressed radar data signals, to apply the compressed radar data signals to a log detector to generate log detector sample values, and to generate a first log cell-average constant false alarm rate (CA-CFAR) threshold from the log detector sample values by computing and adding an average sample value SAVG from the log detector sample values, a probability of false alarm factor ?, and a log CA-CFAR correction factor ?, where the first log CA-CFAR threshold may be used with a second log CA-CFAR threshold to generate an ordered statistics CA-CFAR threshold for the compressed radar data signals by sorting the first and second log CA-CFAR thresholds by magnitude to form a sorted list of log CA-CFAR thresholds, and then selecting a kth threshold from the sorted list of log CA-CFAR thresholds as the OS-CA-CFAR threshold.

Abstract: In accordance with a first aspect, a communication device is provided, comprising: a transmitter configured to transmit one or more radio frequency signal pulses to an external communication device; a receiver configured to receive one or more response signals in response to the radio frequency signal pulses transmitted by the transmitter; a signal analyzer configured to detect one or more characteristics of the response signals, to compare the detected characteristics with predefined reference characteristics and to generate an output indicative of a result of comparing the detected characteristics with the predefined reference characteristics; a processing unit configured to determine at least one category to which the external communication device belongs based on the output generated by the signal analyzer. In accordance with a second aspect, a corresponding method of operating a communication device is conceived. In accordance with a third aspect, a corresponding computer program is provided.

Abstract: A system, method, and apparatus are provided for handling communications with external communication channel hardware devices by a processor executing event-based programming code to interface a plurality of virtual machines with the external communication channel hardware devices by providing the processor with an event latch for storing hardware events received from the external communication channel hardware devices, with a timer circuit that generates a sequence of timer interrupt signals, and with a masking circuit that masks the hardware events stored in the event latch with an event mask in response to each timer interrupt signal, where each event mask is associated with a different virtual machine running on the processor such that each virtual machine is allowed to communicate only on a masked subset of the hardware events specified by the event mask to ensure freedom from interference between the plurality of virtual machines when communicating with the external communication channel hardware device

Abstract: A magnetoresistive random-access memory (MRAM) device includes an array of MRAM bit cells grouped into words, each word having specified number of data bit cells, error correction code (ECC) bit cells, and at least two inversion indicator bit cells, the inversion indicator bit cells being redundant of each other; and a memory controller. The memory controller is configured to, for each of the words, set the inversion indicator bit cells to indicate whether the number of data bit cells in a word having a zero value is greater than the number of data bit cells having a one value, invert the zeroes and ones in the bit cells when the inversion indicator bit cells are set to indicate a greater number of zeroes than ones in the data bit cells of the word, and revert the data bit cells to their value before the zeroes and ones were inverted.

Abstract: A vehicle control device includes a plurality of IC units, while maintaining the operational reliability. The vehicle control device includes an IC unit for performing image processing on outputs from cameras; an IC unit for performing recognition processing of an external environment of the vehicle; and an IC unit for performing judgment processing for cruise control of the vehicle. A control flow is provided so as to allow the IC unit to transmit a control signal to the IC units and. The control flow is provided separately from a data flow configured to transmit the output from the cameras, the image data, and the external environment data.

Abstract: A processing system including processors, peripheral slots, hardware resources, and gateway circuitry. Each processor is assigned a corresponding identifier. The peripheral slots are located within an addressable peripheral space. Each hardware resource is placed into a corresponding peripheral slot, including at least one direct memory access (DMA) device supporting at least one DMA channel and at least one general-purpose input/output (GPIO) pin. Memory protection and gateway circuitry is programmed to control access of the hardware resources only by a processor that provides a matching identifier. The memories along with hardware resources are protected against unauthorized accesses to isolate applications executed on each processor within a multicore system and hence support freedom of interference.

Abstract: A Controller Area Network, CAN, bit stream sampling apparatus for a CAN controller, the apparatus configured to receive a bit stream from a CAN transceiver, the apparatus configured to: detect rising edges in said bit stream; detect, separately, falling edges in said bit stream; and generate a restored non-return-to-zero coded bit stream based at least on said detected falling edges and said detected rising edges.

Abstract: A system includes a first integrated circuit device, a second integrated circuit device, and a reference clock provided to the first and second integrated circuit devices. The first integrated circuit device detects a first edge of a first clock utilized by the first integrated circuit device, detects a second edge of the first clock, determines a first count of cycles of the reference clock between the first edge and the second edge, and communicates the first count to the second integrated circuit device. The second integrated circuit device receives the first count, provides a third edge of a second clock utilized by the second integrated circuit device, determines that a first number of cycles of the reference clock since providing the third edge is equal to the first count, and provides a fourth edge of the second clock in response to determining that the first number of cycles is equal to the first count.

Abstract: A method for self-calibration of reference voltage drop in a Digital to Analog Converter (DAC) includes measuring each one of a plurality of thermometric weightages associated with a respective one of a plurality of thermometric bits, wherein the DAC includes a plurality of sub-binary bits and the plurality of thermometric bits. For each sequentially increasing combination of thermometric bit settings including at least two thermometric bits coupled to a high reference voltage and each sub-binary bit coupled to a low reference voltage, performing the steps of: determining a respective combined weightage correction; adding the combined weightage correction to the highest order bit of the combination of thermometric bit settings; and incrementing a number of bits of the combination of thermometric bit settings in response to the number of bits of the sequential combination being less than a total number of the plurality of thermometric bits.