Abstract: A circuit includes a current mirror stage with a switch, that when made conductive, provides current between the input and the output of the current mirror stage through the switch. When the switch is nonconductive, current is not provided through the switch. The stage includes current mirror circuitry, that when the switch is nonconductive, provides current at the output that is mirrored from current provided to the input of the current mirror stage.

Abstract: A temperature detection circuit includes a first current path and a second current path. The first current path includes a first transistor with a control terminal coupled to receive a reference voltage and includes a temperature sensing device. The second current path includes a second transistor with a control terminal coupled to a node of the first current path. The second current path includes a node that provides an indication of a detected temperature.

Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form bottom gate electrodes having a first gate structure (40A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (46A-B) in the top Si/SiGe superlattice structures.

Abstract: In connection with an RF communication system, exemplary aspects involve a method for use in a communication system in which a first system (e.g., 802.11) that is asynchronously based and which is susceptible to interference from a second system (e.g., synchronous-based LTE-CV2X). Such interference is due to the frequency spectrum used by the first and second systems overlapping. To mitigate interference issues, example methods spreads out the times for messages in the first system, based on information concerning occupancy of the channel, and transmitting them relative to the end of a cycled transmission allocated for use by the second system.

Abstract: Disclosed is a method of operating a low power wireless receiver in which a radio is periodically operable for receive intervals with sleep intervals therebetween and comprising a sleep clock having a sleep clock accuracy. A first transmission or packet is received. Based on a start moment of the first received packet, and an expected interval between packets, a nominal start moment is determined to start the radio for a packet window until a nominal end moment, for receiving a second packet; the packet window duration is extended in dependence on an estimated drift based on the SCA to provide a widened window. A start moment of a second received packet is measured within the widened window. An actual drift is calculated, from the start moment of the second packet; and an actual start moment and an actual window duration is determined, for receiving a third packet, based on the actual drift.

Abstract: There is described a pulse-triggered level shifter circuit comprising: i) a command circuit configured to shift a command input signal of a first voltage domain to a command output signal of a second voltage domain, the command circuit comprising: a) a command input stage for receiving the command input signal, and b) a command output stage for providing the command output signal; and ii) a feedback circuit coupled to the command circuit and configured to shift a feedback input signal of a third voltage domain to a feedback output signal of a forth voltage domain, the feedback circuit comprising: c) a feedback input stage for receiving the command output signal as the feedback input signal, and d) a feedback output stage for providing the feedback output signal. The command circuit and the feedback circuit are hereby integrated into one single level shifter circuit.

Abstract: An apparatus and method for determining location information using a multi-polarized antenna array is disclosed. The multi-polarized antenna array includes a plurality of metal patches and a multiplexer. Each metal patch has at least two feed-points. The multiplexer is coupled to an RF terminal and to each of the at least two feed-points of each of the plurality of metal patches. The antenna array is configurable to couple each feed-point one at a time to the RF terminal. Location information may be determined by a controller coupled to the RF terminal from RF signals received via each feed-point.

Abstract: In a particular example, a low drift voltage reference system includes a Zener diode circuit, a voltage reduction circuit, and a proportional-to-absolute temperature (PTAT) circuit. The Zener diode circuit, which is coupled between a first supply terminal (e.g., VDD) and a second supply terminal (e.g., common), provides an input reference voltage level. The voltage reduction circuit provides another reduced version of the input reference voltage level. The PTAT circuit has first and second differential paths to provide an output reference voltage at an output node of the PTAT circuit, and a feedback path to draw feedback current from the output node to control the differential circuit.

Abstract: One example discloses a near-field communications device, including: a near-field antenna; a conformal material having a first surface and a second surface; wherein the first surface is dielectrically coupled to the antenna; and wherein the second surface is configured to be galvanically coupled to a host-structure.

Abstract: The disclosure relates to determining a carrier phase shift between a first transceiver and a second transceiver, each transceiver comprising a local oscillator for generating a carrier signal, an example method for which comprises: the first transceiver generating and transmitting a first continuous wave carrier signal packet; the second transceiver receiving the first continuous wave carrier signal packet; the second transceiver calculating a first phase correction based on a comparison between the received first continuous wave carrier signal packet and a local oscillator carrier signal at the second transceiver; the second transceiver generating and transmitting a second continuous wave carrier signal packet; the first transceiver receiving the second continuous wave carrier signal packet; the first transceiver calculating a second phase correction based on a comparison between the received second continuous wave carrier signal packet and a local oscillator signal at the first transceiver; and the first t

Abstract: A microelectromechanical systems (MEMS) accelerometer comprises a compliant spring structure with a first beam, a second beam, and a rigid structure. One end of the first beam and one end of the second beam are coupled to the rigid structure and a proof mass is coupled to another end of the second beam. Further, a spring anchor is coupled to another end of the first beam. In response to the proof mass moving, an extension coupled to the rigid structure moves in an opposite direction to motion of the proof mass to contact the proof mass and stop the movement of the proof mass.

Abstract: A method for dynamic enhancement of loop response upon recovery from fault conditions includes detecting a fault condition in response to a programmed output voltage of a Pulse Width Modulation (PWM) converter decreasing below an input voltage of the PWM converter. A peak voltage is sampled at the end of at least one of a plurality of clock cycles of the PWM converter in response to detecting the fault condition, wherein the peak voltage is proportional to a sensed current conducted through a transistor. An error output of an error amplifier is preset to an error value determined by the peak voltage. A PWM driver is controlled with the error value to drive the transistor. An output load is charged to the programmed output voltage with the transistor in response to the input voltage increasing above the programmed output voltage.

Abstract: A system-on-chip (SoC) includes a memory, a trust provisioning system, a one-time programmable (OTP) element, and a comparator. The memory is configured to store a first secret key before an execution of a trust provisioning operation. The trust provisioning system is configured to receive an encrypted version of a first set of secure assets and one of a second secret key and an encrypted version of the second secret key, and execute the trust provisioning operation on the SoC to store the first set of secure assets and the second secret key in the OTP element. The comparator is configured to compare the first and second secret keys to generate a valid signal that is indicative of a validation of the trust provisioning operation. The first set of secure assets and a second set of secure assets associated with the SoC are accessible based on the valid signal.

Abstract: In accordance with a first aspect of the present disclosure, a method is conceived for providing a digital representation of a transaction card in a mobile device, comprising: detecting, by a near field communication unit of said mobile device, that the transaction card is in proximity of the mobile device; upon or after said detecting, performing, by a processing unit of said mobile device, the following steps: retrieving the digital representation of the transaction card from a digitization server; loading the digital representation of the transaction card into a memory of the mobile device; activating the digital representation of the transaction card for a predefined validity period; invalidating the digital representation of the transaction card if no successful near field communication transaction has been performed within said validity period. In accordance with other aspects of the present disclosure, a corresponding computer program and a corresponding mobile device are provided.

Abstract: Disclosed is a method for designing an integrated circuit, wherein the integrated circuit is to be structured in cells, wherein the cells are to comprise functional cells and spare cells. The method comprises: a) designing at least one functional cell; and b) placing a plurality of functional cells on associated pattern positions of an, in particular regular, pattern matrix designed for the functional cells. The method further comprises c) placing, on at least one of the remaining pattern positions of the pattern matrix and instead of at least one spare cell conceivable for the at least one of the remaining pattern positions of the pattern matrix, a gate-based decoupling cell, and alternatively or in addition, d) placing, in at least one gap between pattern positions of the matrix pattern and instead of at least one filler cell conceivable for the at least one gap between pattern positions of the pattern matrix, a gate-based decoupling cell.

Abstract: Various embodiments relate to a method and system for resuming a secure communication session with a server by a device, including: sending a message to the server requesting the resumption of a secure communication session; receiving from the server a server identifier, a server nonce, and a salt; determining that the device has a shared key with the server based upon the server identifier; determining that the received salt is valid; calculating a salted identifier based upon the shared key and the salt; sending the salted identifier to the server; and resuming the secure communication session with the server.

Abstract: A nanosheet semiconductor device and fabrication method are described for integrating the fabrication of nanosheet transistors (71) and capacitors/sensors (72) in a single nanosheet process flow by forming separate transistor and capacitor/sensor stacks (12A-16A, 12B-16B) which are selectively processed to form gate electrode structures (68A-C) which replace remnant SiGe sandwich layers in the transistor stack, to form silicon fixed electrodes using silicon nanosheets (13C, 15C) on a first side of the capacitor/sensor stack, and to form SiGe fixed electrodes using SiGe nanosheets (12C, 14C, 16C) from the middle of remnant SiGe sandwich layers in the capacitor/sensor stack (e.g., 16-2) which are separated from the silicon fixed electrodes by selectively removing top and bottom SiGe nanosheets (e.g., 16-1, 16-3) from the remnant SiGe sandwich layers in the capacitor/sensor stack.

Abstract: It is described a tamper detection device for detecting tampering with respect to a packaging, the device comprising: i) a first electrode comprising a first patterned structure, and ii) a second electrode comprising a second patterned structure. The first electrode and the second electrode are arranged so that the first patterned structure and the second patterned structure are at least partially opposite to each other. In a first arrangement state of the first patterned structure and the second patterned structure with respect to each other, a first capacitance is measurable, in a second arrangement state of the first patterned structure and the second patterned structure with respect to each other, a second capacitance is measurable, wherein the first capacitance is different from the second capacitance, and wherein the first arrangement state is different from the second arrangement state.

Abstract: A system to facilitate communication of a critical signal between functional circuitries of a system-on-chip utilizes a dynamic pattern to securely communicate the critical signal. The system includes selection and comparison circuits. The selection circuit is configured to select and output a set of dynamic pattern bits or a set of fixed reference bits, based on a logic state of the critical signal that is received from one functional circuitry. The comparison circuit is configured to output an output signal based on the set of dynamic pattern bits, and a set of intermediate bits that is derived from the set of dynamic pattern bits or the set of fixed reference bits. The output signal is provided to the other functional circuitry when a logic state of the output signal matches the logic state of the critical signal, thereby securely communicating the critical signal to the other functional circuitry.

Abstract: A data processing system includes a memory configured to receive memory access requests. Each memory access request having a corresponding access address and having a corresponding parity bit for an address value of the corresponding access address. The corresponding access address is received over a plurality of address lines and the parity bit is received over a parity line. The memory includes a memory array having a plurality of memory cells arranged in rows, each row having a corresponding word line of a plurality of word lines, and a row decoder coupled to the plurality of address lines, the parity line, and the plurality of word lines. The row decoder is configured to selectively activate a selected word line of the plurality of word lines based on the corresponding access address and the corresponding parity bit of a received memory access request.