Abstract: A data processing system comprises a Flash memory (120) having a storage space partitioned in a plurality of storage pages (P?). Each storage page comprises a memory reliability indicator indicative for the reliability of a storage region of the memory. Coupled to the Flash memory is a controller (150) for the Flash memory, that includes a facility for protecting data against errors occurring during storage in the Flash memory and for detecting and/or correcting errors in the data stored in the data, when retrieved from the Flash memory. A data processing unit (100) is coupled to the controller (150) that has access to a working page (P) comprising a first section of user data and a second section of management information, including a memory reliability indicator. The data processing system is characterized by a data re-arranging facility (105) for subdividing the data in the work page into a plurality of portions.

Abstract: A MEMS switch comprises a substrate, first and second signal lines over the substrate, which each terminate at a connection region, a lower actuation electrode over the substrate and movable contact electrode suspended over the connection regions of the first and second signal lines. An upper actuation electrode is provided over the lower actuation electrode. The connection regions of the first and second signal lines are at a first height from the substrate, wherein signal line portions extending from the connection regions are at a lower height from the substrate, and the lower actuation electrode is provided over the lower height signal line portions, so that the lower height signal line portions are buried. The area available for the actuation electrodes becomes larger and undesired forces and interference are reduced.

Abstract: Various embodiments relate to a reconfigurable integrated digital Chireix out-phasing power amplifier for use in high power base stations is described and a related method of said design. The power amplifier may include a power transistor circuitry having plurality of power transistors and shunt-series circuitry (L1C1, L2C2), a broadband combiner having Chireix compensation elements, and an impedance matching filter. The power transistor circuitry, the broadband combiner, and the impedance matching filter are integrated in a unified package. In one embodiment, the power amplifier is implemented in a real switch-mode to facilitate integration of the Chireix compensation elements so as to make the Chireix power amplifier tunable. A method of driving Chireix power amplifier structure is also described.

Abstract: A transformer comprising primary and secondary windings is disclosed. Each winding has first and second metal capping layers coupled together electrically in parallel by a metal connector passing through a substrate lying between the first and second metal capping layers.

Abstract: Various embodiments relate to a reconfigurable integrated digital Chireix out-phasing power amplifier for use in high power base stations is described and a related method of said design. The power amplifier may include a power transistor circuitry having plurality of power transistors and shunt-series circuitry (L1C1, L2C2), a broadband combiner having Chireix compensation elements, and an impedance matching filter. In one embodiment, the power amplifier is implemented in a real switch-mode to facilitate integration of the Chireix compensation elements so as to make the Chireix power amplifier tunable. A method of driving Chireix power amplifier structure is also described. In some embodiments, a variable supply voltage may power the transistor circuitry based on the desired output power of the Chireix power amplifier. In some embodiments, the variable supply voltage may depend upon an out-phasing angle between the two drivers in the transistor circuitry.

Abstract: An energy storage device (300), the device (300) comprising a substrate (102), a steric structure (104) formed on and/or in a main surface (106) of the substrate (102), a current collector stack (202) formed on the steric structure (104), and an electric storage stack (302) formed on the current collector stack (202), wherein side walls (108) of the steric structure (104) and the main surface (106) of the substrate (102) enclose an acute angle of more than 80 degrees.

Abstract: It is disclosed a semiconductor transistor, comprising a semiconductor substrate (111) in which a channel region (115) and a drain extension region (119) connected to the channel region are provided; a gate electrode (127) configured to provide an electric field for influencing the channel region; a first electrically conductive shield element (131) extending in a horizontal direction (103) parallel to a main surface of the semiconductor substrate and being arranged beside the gate electrode spaced apart from the drain extension region in a vertical direction (105) perpendicular to the horizontal direction; and a second electrically conductive shield element (133) arranged spaced apart from the first shield element in the vertical direction, wherein the gate electrode protrudes over the first shield element in the vertical direction.

Abstract: Digital spur reduction in which spurs are kept outside selected channels of interest. An integrated radiofrequency transceiver circuit has digital and analogue components, the circuit includes a radiofrequency signal receiver having a local oscillator signal generator configured to provide a local oscillator signal at a frequency fLO and a mixer configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal; and a clock signal generator configured to generate a digital clock signal at a frequency fDIG for operation of the digital components, where the local oscillator signal and/or a reference signal from which the local oscillator signal is derived are generated such that digital spurs lie outside a band selected by the receiver.

Abstract: An integrated circuit die includes a plurality of interconnects including a first test data input, a second test data input and a test dat a output, and a test arrangement for testing the integrated circuit die. The test arrangement includes a further multiplexer coupled to the test data output, a multiplexer coupled to the first test data input and the second test data input, a plurality of shift registers including an instruction register, each of the shift registers being coupled between the multiplexer and the further multiplexer and a controller for controlling the multiplexer and the further multiplexer in response to the instruction register. Such a test arrangement facilitates JTAG compliant testing of a system in package by providing a direct connection between the SiP test data input pin and the second test data input of the IC die, and the SiP test data output pin and the test data output of the IC die, thus facilitating the bypassing of other test arrangements in the SiP.

Abstract: A Power Factor Corrector (PFC), typically used as the first stage of switched mode power supplies, particularly suited for Universal Mains inputs, is disclosed, along with methods for controlling a switched mode power supply having power factor correction. In order to increase efficiency, particularly under low load conditions, without undue degradation of the Power Factor, the switching of the PFC circuit is confined to one or more operating windows within each half-cycle. In embodiments, the operating window comprises a small time window centred around the peak of the mains voltage. The higher the power level, the wider the switching window.

Abstract: Digital spur reduction in which spurs are kept outside selected channels of interest, with illustrative embodiments relating to an integrated radiofrequency transceiver circuit having digital and analogue components, the circuit having a radiofrequency signal receiver with a local oscillator signal generator configured to provide a local oscillator signal at a frequency fLO and a mixer configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal; and a clock signal generator configured to generate a digital clock signal at a frequency fDIG for operation of the digital components, where the local oscillator signal and/or a reference signal from which the local oscillator signal is derived are generated such that digital spurs lie outside a band selected by the receiver.

Abstract: The present invention relates to a sensing device with a surface having at least one individual sensing region, wherein each sensing region includes a plurality of binding elements anchored on the surface for binding different specific analytes of interest, at least one of the analyte of interest and its matching binding element having a label for detecting said binding. The present invention further relates to a method of manufacturing such a sensing device.

Abstract: A method of manufacturing a transistor device (600), wherein the method comprises forming a trench (106) in a substrate (102), only partially filling the trench (106) with electrically insulating material (202), and implanting a collector region (304) of a bipolar transistor (608) of the transistor device (600) through the only partially filled trench (106).

Abstract: A method for controlling burst mode operation of a switched mode power supply (SMPS) is disclosed.

Abstract: The invention relates to a method and an apparatus (1) for the timing of signals (2), preferably of signals (2) including fast changing disturbances, the apparatus (1) comprising a first timer (3) and a second timer (4), the first timer (3) is characterised by a first decay time (5) and first attack time (5) and the second timer (4) is characterised by a second decay time (6) and second attack time (6), the second attack time and the second decay time are faster than the first attack time and the first decay time and wherein an input signal (2) will be treated in parallel by the first timer (3) and second timer (4).

Abstract: The invention refers to an amplifier (1) comprising a switchable capacitive divider (10) for dividing a supply voltage delivered to the amplifier (1), the switchable capacitive divider being coupled to a coupling circuit (15) via a first wire and a second wire, the coupling circuit determining a connection path between said first and second wire and a first capacitor (C2) and a switchable power circuit (20).

Abstract: In an I-Q receiver, I-Q baseband mixer receives a real signal, and outputs an in-phase baseband information signal and a quadrature baseband information signal, a decoupling compensator multiplies in-phase baseband information signal and the quadrature baseband information signal by a trained decoupling matrix that, based on adaptive training in response to purely in-phase and purely quadrature phase training signals, decouples the in-phase baseband information signal from a quadrature component of the I-Q signal, and decouples quadrature-phase baseband information signal from an in-phase component of the I-Q signal. Optionally, a trained I-arm-Q-arm imbalance compensator performs a filter compensation on one or both of the decoupled in-phase baseband signal and the quadrature-phase baseband signal output by the trained decoupling matrix.

Abstract: The present invention, generally speaking, provides interleavers and methods of interleaving that satisfy the need for backward compatibility while effectively addressing competing design objectives. In accordance with one aspect of the invention, data is transmitted using a number of transmit antennas greater than an expected number of receive antennas. At least one pair of transmit antennas (ant?—1, ant?_N) is formed, and multiple second data streams (610a, 610u) are formed from a first data stream, successive bits in said first data stream being assigned to different ones of said second data streams. Block interleaving of multiple respective ones of said second data streams is individually performed (611a, 611u). During successive transmission intervals (617), the pair of transmit antennas is used to transmit a pair of data symbols taken from different ones of said second data streams, followed by an equivalent transformed pair of data symbols.

Abstract: A pre-driver for an amplifier comprising a load network in which the following elements are connected in the following order: a resistor-an inductor-a capacitor. Also described are a power amplifier comprising such a pre-driver, a method of fabricating a pre-driver for an amplifier, and a method of performing power amplification.

Abstract: An arrangement (30) and a method for digitally filtering a time-discrete digital signal, wherein the signal is transformed to the frequency domain using discrete Fourier transformation (31), the signal is filtered in the frequency domain (33), wherein a filter response can be adapted in real time as required to respond to changes in the interference environment, and the filtered signal is transformed back to the time domain using inverse discrete Fourier transformation (32) to create an output signal, and wherein bin frequencies of said signal in the frequency domain are translated by a real amount and the sampling rate of the output signal is changed by a real factor.