Abstract: The invention relates to a method for selective deposition of Si or SiGe on a Si or SiGe surface. The method exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.

Abstract: Methods for manufacturing a bipolar transistor semiconductor device are described, along with devices fabricated in accordance with the methods. The methods include the steps of forming a stack of layers over a semiconductor body comprising a window definition layer (18,38), a layer (20) of semiconductor material, a first insulating layer (22), and a second insulating layer (24) which is selectively etchable with respect to the first insulating layer. A trench (26) is then etched into the stack down to the window definition layer. The portion of the trench extending through the second insulating layer is widened to form a wider trench portion (28) therethrough. A window (36) is defined in the window definition layer which is aligned with the wider trench portion, and serves to define the base-collector or base-emitter junction in the finished device.

Abstract: A program (MC), which can be executed by a programmable circuit, is protected in the following manner. An instruction block (IB) is provided on the basis of at least a portion (MC-P) of the program. A protective code (DS) is generated that has a predefined relationship with the instruction block (IB). The instruction block (IB) is analyzed (ANL) so as to identify free ranges (FI) within the instruction block that are neutral with respect to an execution of the instruction block. The free ranges comprise at least one of the following types: bit ranges and value ranges. The free ranges that have been identified are used for embedding (SEB) the protective code (DS) within the instruction block (IB).

Abstract: A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.

Abstract: The light dose received by perishable goods is an important parameter in determining the lifetime of those goods. A light sensor (30) is described having a photosensitive element (18) which changes its material property according to the light dose received. This change can be detected electrically by electrodes (12, 14) in the light sensor. Because the change in material property is permanent, this removes the need for a memory to store a value representing the light dose received by the light sensor.

Abstract: A crystalline semiconductor resonator device comprises two matched resonators which are aligned differently with respect to the crystal structure of the crystalline semiconductor. The resonators each comprise a portion of a material having a different temperature dependency of the Young's modulus to the temperature dependency of the Young's modulus of the crystalline semiconductor material. In this way, the suspension springs for the resonators have different properties, which influence the resonant frequency. The resonant frequency ratios between the first and second resonators at a calibration temperature and an operation temperature are measured. A frequency of one (or both) of the resonators at the operation temperature can then be derived which takes into account the temperature dependency of the one of the resonators.

Abstract: A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module is used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.

Abstract: In example embodiment, there is an integrated circuit (IC) device (5) assembled in a package (5) having a plurality of die including a first device (20) and at least one additional device (30). The IC comprises a substrate (10). A first device die (20), having bonding pads including ground connections, is die attached to the substrate (10). An additional device die (30), having bonding pads including ground connections is disposed on top of the first device die (20). The additional device die is die attached to the first device die. The ground connections of the first device die are connected to the ground connections of the additional device die in order to minimize the electrical interference between the device dies. An additional feature of the embodiment is, ground connections of the first device are connected to the ground connections of the additional device with a conductive adhesive (25).

Abstract: An ESD protection circuit comprises a first supply line (VDD), a second supply line (Vss), an ESD protection device, preferably being configured as a transistor (MP), which is connected between the first and second supply line (VDD, VSS) and at least one pin (VA) connected to the first and second supply lines (VDD, VSS) via diodes D1, D2. The ESD protection device is controllable by a trigger voltage that is set by a trigger voltage setting circuit (RP, RD, Z1, Z2, Z3). The ESD protection circuit comprises a trigger circuit (1) being connected to the at least one pin (VA) and providing pin specific trigger voltages, wherein the trigger circuit (1) is further connected to the trigger voltage setting circuit.

Abstract: An integrated circuit arrangement has a processor array (2) with processor elements (4) and a memory (6) with memory elements (8) arranged in rows (32) and columns (30). The columns (30) of memory elements (8) are addressed by respective processor elements (4). An input sequencer (14) and feedback path (24) cooperate to reorder input data in the memory (6) to carry out both block and line based processing.

Abstract: A demodulator (6) for demodulating a modulated signal (3) comprises a Hubert transformer (7) for generating a Hubert transformed modulated signal (18) of the modulated signal (3). The Hubert transformed modulated signal (18) comprises modulated (5) and unmodulated signal sequences (4) and originates from an unmodulated signal. The demodulator (6) further comprises a comparing device (14) for comparing the Hubert transformed modulated signal (18) with a reference signal (15), which corresponds to the Hubert transformed unmodulated signal. The demodulator (6) is further configured to identify the modulated and unmodulated signal sequences (4, 5) based on the comparison.

Abstract: A method and apparatus for a tuner for adjusting the receiver bandwidth based on adjacent channel interference and group delay distortion.

Abstract: A transmitter/receiver circuit comprises a wireless transmission/reception circuit having a first inductor for generating/detecting a magnetic induction field onto which an output of a radio frequency circuit is modulated and a second inductor in series with the first inductor for generating/detecting an electric induction field onto which the output of the radio frequency circuit is modulated. The second inductor comprises an electrically conductive track which at least partially surrounds a grounded electrically conductive core. The invention thus provides the transmitter and receiver for a communication system using near fields, and in which the input/output of the radio frequency circuitry can be balanced. The first coil produces the main magnetic induction field and the second coil is activated as an antenna producing an electric induction field. By this method, the operating range is increased and the relative positioning between both communication ends is less sensitive.

Abstract: Disclosed is an integrated circuit comprising an electrode arrangement for detecting the presence of a liquid, said electrode arrangement comprising a first electrode and a second electrode, wherein, prior to exposure of the electrode arrangement to said liquid, a surface of at least one of the first electrode and second electrode is at least partially covered by a compound that is soluble in the liquid; the electrical properties of the electrode arrangement being dependent on the amount of the compound covering said surface. An package and electronic device comprising such an IC and a method of manufacturing such an IC are also disclosed.

Abstract: A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.

Abstract: A non-volatile memory cell (200) comprising a floating gate transistor (206) comprising a floating gate (10) positioned between a control gate (14) and a first channel region (232) and an access gate transistor (208) comprising an access gate (22) and a second channel region (234), the first channel region (232) comprising a first implant (242) with a first dosage level (234), and the second channel region comprising a second implant (244) having a second dosage level, the first dosage level being less than the second dosage level.

Abstract: A system and method for transmitting a baseband real signal with a non-constant envelope using a polar transmitter involves decomposing a baseband real signal into a non-constant envelope signal of the baseband real signal and a sign signal of the baseband real signal, where the sign signal restores zero crossing regions of the non-constant envelope signal, modulating a carrier signal with the sign signal of the baseband real signal to generate a modulated signal, converting the non-constant envelope signal of the baseband real signal into a voltage signal using a voltage controlled supply regulator, amplifying the modulated signal into an amplified signal based on the voltage signal, and transmitting the amplified signal to an external wireless device.

Abstract: The invention refers to a Doherty power amplifier comprising a first power amplifier (Main PA) adapted to receive an input signal and adapted to provide a first output signal which is phase shifted with respect to the input signal. The amplifier further comprises a second power amplifier (Peak PA), adapted to receive a phase shifted input signal and adapted to provide a second output signal. The power amplifier is characterized in that at least one of the first or the second power amplifiers comprises a first driver power amplifier (T1) comprising a first gate input and a first drain output. The first driver power amplifier (T1) is coupled to a first output power amplifier (T2) comprising a second gate input and a second drain output. The first gate input and the second gate input are adapted to receive a control signal, the control signal being obtained after an envelope detection provided by an envelope detector coupled to the input signal.

Abstract: System and method for compensating for changes in an output impedance of a power amplifier uses an impedance compensating circuit with an impedance inverter coupled to the power amplifier. The impedance inverter of the impedance compensating circuit is configured such that an output impedance of the impedance inverter is proportional to the inverse of the output impedance of the power amplifier to compensate for changes in the output impedance of the power amplifier.

Abstract: A sensor, electrically connected to transponder, is calibrated in an environment of operational use of the transponder. The calibrating uses as a reference a value of a parameter representative of the environment.